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Altera
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| Part No. |
EP1S20F484
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| OCR Text |
...d I/O standard output pin delay adders for loading in Table 4-102. Added spec for FPLL[10..7]CLK pins in Tables 4-104 and 4-107. Updated high-speed I/O specification for J=2 in Tables 4-114 and 4-115. Updated EPLL specification and fast PLL... |
| Description |
FPGA (Field-Programmable Gate Array)
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| File Size |
1,369.20K /
260 Page |
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it Online |
Download Datasheet
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Xilinx, Inc.
XILINX[Xilinx, Inc]
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| Part No. |
XCR3128XL XCR3128XL-7CS144C XCR3128XL-7CS144I XCR3128XL-7TQ144C XCR3128XL-7VQ100I XCR3128XL-10CS144C XCR3128XL-10CS144I XCR3128XL-10TQ144I XCR3128XL-10VQ100C XCR3128XL-10VQ100I XCR3128XL-6CS144C XCR3128XL-6CS144I XCR3128XL-6TQ144C XCR3128XL-6TQ144I XCR3128XL-6VQ100C XCR3128XL-6VQ100I XCR3128XL-7TQ144I XCR3128XL-7VQ100C XCR3128XL-SERIES XCR3128XL-10TQ144C
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| OCR Text |
...IA delay 1.7 2.1 3.0 ns
Time adders TLOGI3 TUDA TSLEW Fold-back NAND delay Universal delay Slew rate limited delay 6.0 1.7 4.0 Advance
Notes: 1. These parameters guaranteed by design and/or characterization, not testing. 2. See XPLA fam... |
| Description |
XCR3128XL 128 Macrocell CPLD EE PLD, 7.5 ns, PQFP100
XCR3128XL 128 Macrocell CPLD EE PLD, 6 ns, PBGA144
XCR3128XL 128 Macrocell CPLD EE PLD, 10 ns, PQFP144
T1/E1 Transformer EE PLD, 10 ns, PQFP100
From old datasheet system
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| File Size |
79.96K /
10 Page |
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it Online |
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