Description |
14-bit Registered buffer With SSTL_2 Inputs and Outputs 48-TVSOP 0 to 70 100万1812k × 32的,12k × 36 35.7同步突发静态存储器<br>1M x 18, 512K x 32, 512K x 36 18Mb Sync burst SRAMs 1M×18512k×32512k×36 18M位同步突发静态存储器<br>20-bit SSTL_3 Interface buffer With 3-State Outputs 64-TSSOP 0 to 70 100万1812k × 32的,12k × 36 35.7同步突发静态存储器<br>25-bit configurable Registered buffer With Address-Parity Test 96-LFbGA 0 to 70 100万1812k × 32的,12k × 36 35.7同步突发静态存储器<br>1M x 18, 512K x 32, 512K x 36 18Mb Sync burst SRAMs 1M×1812k×3212k×36 18M位同步突发静态存储器<br>Quad 2-input Exclusive-OR gates 14-PDIP 0 to 70 100万1812k × 32的,12k × 36 35.7同步突发静态存储器<br>25-bit configurable Registered buffer with SSTL_18 Inputs and Outputs 96-LFbGA 0 to 70 100万1812k × 32的,12k × 36 35.7同步突发静态存储器<br>20-bit SSTL_3 Interface Universal bus Driver With 3-State Outputs 64-TSSOP 0 to 70<br>Quad 2-input Exclusive-OR gates 14-SOIC 0 to 70<br>13-bit to 26-bit Registered buffer with SSTL_2 Inputs and Outputs 56-VQFN 0 to 70<br>
|