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ALSC
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| Part No. |
AS90L10208
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| OCR Text |
...at a frequency of up to 800 MHz ddr for both transmit and receive directions and sustains a total aggregate bandwidth up to 25.6 Gbps per 8-...dual-hosted chain. One 64-bit configurable PCI/PCI-X1.0 port: * 1 x 64 bit, up to 66 MHz PCI 2.2 or ... |
| Description |
HyperTransport Bridges
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| File Size |
127.35K /
2 Page |
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Maxim
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| Part No. |
MAX1917EVKIT
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| OCR Text |
...e power-management solution for ddr memory. This EV kit is a fully assembled and tested circuit board. The MAX1917 EV kit generates a regula...dual-trace oscilloscope The MAX1917 EV kit is a fully assembled and tested surface-mount board. Foll... |
| Description |
Evaluation Kit for the MAX1917
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| File Size |
156.29K /
4 Page |
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ONSEMI
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| Part No. |
NCP5209
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| OCR Text |
ddr Power Controller
The NCP5209 4-In-1 PWM Buck and Tri-Linear Power Controller is a complete ACPI compliant power solution for MCH and DD...dual Supply Input Gate Driver Input Supply. A Boost Capacitor is Connected between SWDDQ and BOOT. G... |
| Description |
4-In-1 PWM Buck and Tri-Linear ddr Power Controller
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| File Size |
82.00K /
12 Page |
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ALSC
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| Part No. |
AS95L2100
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| OCR Text |
...stems.
Device Block Diagram
ddr SRAM Interface
RPR MAC
Adaptive Header Engine Receive Queue
Line-Side Port A SFI-4
OC-192 Framer...dual SPI4.2 Interface SPI4.2
Scheduler Line-Side Port B SFI-4
OC-192 Framers Quad OC-48 Framers ... |
| Description |
Resilient Packet Ring Controllers?
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| File Size |
146.99K /
4 Page |
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ICS
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| Part No. |
ICS952004
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| OCR Text |
...-16 as the memory buffer. * For ddr SDRAM system use the ICS93705 or ICS93722 as the memory buffer. * Uses external 14.318MHz crystal. Key S...dual function input pin for Vtt_PWRGD and PD# signal. When Vtt_PWRGD goes high the frequency select ... |
| Description |
Programmable Timing Control Hub for P4 Processors (P)
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| File Size |
172.05K /
20 Page |
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it Online |
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MAXIM[Maxim Integrated Products]
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| Part No. |
MAX1540 MAX1541 MAX1540ETJ MAX1541ETL
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| OCR Text |
...Voltage Core Supplies (MAX1541) ddr Memory Termination (MAX1541) Active Termination Buses (MAX1541)
Pin Configurations
CSN1
CSP1
ON1...dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540/... |
| Description |
dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
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| File Size |
831.57K /
49 Page |
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Xilinx
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| Part No. |
XC3S5000 XC3S400 XC3S4000 XC3S2000
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| OCR Text |
...4V to 3.45V - Double Data Rate (ddr) support - ddr, ddr2 SDRAM support up to 333 Mbps Logic resources - Abundant logic cells with shift regi...dual-port blocks. * * Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the... |
| Description |
(XC3S50 - XC3S5000) Spartan-3 FPGA Family
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| File Size |
1,763.79K /
204 Page |
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it Online |
Download Datasheet |
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Price and Availability
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