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Altera Corporation
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| Part No. |
EP1K30FC256 ACEX1K07
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| OCR Text |
... DesignWare components, Verilog hdl, Vhdl, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic
Table 2. ACEX 1K Package Optio... |
| Description |
Programmable Logic Family
From old datasheet system
Field Programmable Gate Array (FPGA)
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| File Size |
828.19K /
88 Page |
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it Online |
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Cypress
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| Part No. |
CY3120J CY3120 3120
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| OCR Text |
...on
Warp2 is a state-of-the-art hdl compiler for designing with Cypress's Complex Programmable Logic Devices (CPLDs). Warp2 utilizes a subset of IEEE 1076 and 1164 Vhdl as its Hardware Description Language (hdl) for design entry. Warp2 acce... |
| Description |
Warp2Vhdl Compiler for CPLDs
From old datasheet system
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| File Size |
121.82K /
6 Page |
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it Online |
Download Datasheet |
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Cypress
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| Part No. |
CY3140 3140
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| OCR Text |
...t design entry formats: -- ABEL-hdl for ABEL-4, ABEL-5, and ABEL-6 -- Schematic entry, Vhdl, and ABEL-hdl for SynarioTM * Full integration supporting all ABELTM and SynarioTM design features * Supports the full family of FLASH370iTM devices... |
| Description |
ABELSynario Design Kit for FLASH370i
From old datasheet system
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| File Size |
21.36K /
1 Page |
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it Online |
Download Datasheet |
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Cypress
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| Part No. |
CY3112J 3110
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| OCR Text |
...on
Warp2 is a state-of-the-art hdl compiler for designing with Cypress's Complex Programmable Logic Devices (CPLDs). Warp2 utilizes a subset of IEEE 1364 Verilog as its Hardware Description Language (hdl) for design entry. Another design e... |
| Description |
Warp2 Verilog Development System for CPLDs DESIGN ENTRY COMPILATION VERFICA TION
From old datasheet system
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| File Size |
94.00K /
5 Page |
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it Online |
Download Datasheet |
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Price and Availability
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