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ICS
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| Part No. |
ICS873034
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| OCR Text |
...rs and the outputs are enabled. lvcmos/LVTTL interface levels. Bias voltage. Pullup/ Clock input. Defaults to VCC/2 (.66) when left open. LVPECL interface levels. Pulldown Pulldown Clock input. Default LOW when left floating. LVPECL interfa... |
| Description |
Low Skew, ÷2, ÷4, ÷8, Differential-to-LVPECL Clock Generator. Industrial Temperature.
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| File Size |
256.16K /
16 Page |
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ICS
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| Part No. |
ICS8732-01
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| OCR Text |
...ble differential CLK0, nCLK0 or lvcmos/LVTTL CLK1 inputs * CLK0, nCLK0 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * CLK1 accepts the following input levels: lvcmos or LVTTL * Maximum output frequency: 350MHz * VCO ... |
| Description |
Low Skew, 1-to-10, LVPECL Clock Multiplier/Zero Delay Buffer
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| File Size |
145.68K /
16 Page |
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ICS
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| Part No. |
ICS87322BI
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| OCR Text |
...rs and the outputs are enabled. lvcmos / LVTTL interface levels. Selects divide value for Bank A output as described in Table 3C. lvcmos / LVTTL interface levels. Selects divide value for Bank B output as described in Table 3C. lvcmos / LVT... |
| Description |
Low Skew, ÷1, ÷2 Clock Generator. Industrial Temperature.
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| File Size |
149.45K /
15 Page |
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ICS
Integrated Device Technology, Inc.
INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
M1020 M1021 M1021-13-161.1328LF M1021-13I161.1328LF M1020-11-155.5200LF M1020-11I167.3280LF
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...LVPECL, as well as single-ended lvcmos, LVTTL Loss of Lock (LOL) output pin Narrow Bandwidth control input (NBW pin) Hitless Switching (HS) options with or without Phase Build-out (PBO) to enable SONET (GR-253) / SDH (G.813) MTIE and TDE... |
| Description |
Frequency Translation PLL Family with Loss of Lock indicator and Hitless Switching options
ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36 9 X 9 MM, CERAMIC, LCC-36
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| File Size |
307.50K /
10 Page |
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Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
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| Part No. |
MAX9173
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| OCR Text |
...l inputs and translates them to lvcmos/LVTTL outputs. The MAX9173 inputs are high impedance and require an external termination resistor when used in a point-topoint connection. The device supports a wide common-mode input range of 0.05V to... |
| Description |
Quad LVDS Line Receiver with Flow-Through Pinout and ?n-PathFail-Safe 四路LVDS线接收器，引脚按信号流向排列，带有通道失效保护
Quad LVDS Line Receiver with Flow- Through Pinout and “In-Path?Fail-Safe
Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe
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| File Size |
337.24K /
14 Page |
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MAXIM - Dallas Semiconductor
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| Part No. |
MAX9324
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| OCR Text |
lvcmos Output Clock and Data Driver
General Description
The MAX9324 low-skew, low-jitter, clock and data driver distributes a differential...LVTTL Clock Output. SEOUT reproduces CLK when SEOUT_Z = GND. SEOUT goes high impedance when SEOUT_Z ... |
| Description |
One-to-Five LVPECL/lvcmos Output Clock and Data Driver
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| File Size |
270.02K /
12 Page |
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Price and Availability
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