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  endpoint Datasheet PDF File

For endpoint Found Datasheets File :: 1555    Search Time::1.219ms    
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    ST Microelectronics
Part No. ST7FSCR1E4M1
OCR Text ...ne 8-byte bidirectional control endpoint one 64-byte in endpoint, one 64-byte out endpoint four 8-byte in endpoints 35 or 4 i/o ports : ? up to 4 led outputs with software program- mable constant current (3 or 7 ma). ? 2 general purpo...
Description 8-BIT LOW-POWER, FULL-SPEED USB MCU WITH 16K FLASH, 768 RAM, SMARTCARD I/F, TIMER

File Size 836.60K  /  103 Page

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    ST Microelectronics
Part No. ST72PSCR1R4M1 ST72PSCR1R4T1 ST72PSCR1X4M1 ST72PSCR1X4T1 ST7PSCR1E4M1 ST7SCR1E4M1 ST72FSCR1R4T1
OCR Text ...ne 8-byte bidirectional control endpoint one 64-byte in endpoint, one 64-byte out endpoint four 8-byte in endpoints n 35 or 4 i/o ports : C up to 4 led outputs with software program- mable constant current (3 or 7 ma). C 2 general purp...
Description 8-BIT LOW-POWER, FULL-SPEED USB MCU WITH 16K FLASH, 768 RAM, SMARTCARD I/F, TIMER

File Size 1,014.78K  /  102 Page

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    TMP92CH21FG

Toshiba Semiconductor
Part No. TMP92CH21FG
OCR Text ... not supported.) endpoints spec endpoint 0: Control 64 bytes* 1-FIFO endpoint 1: BULK (out) 64 bytes* 2-FIFO endpoint 2: BULK (in) 64 bytes* 2-FIFO endpoint 3: Interrupt (in) 8 bytes* 1-FIFO * * * * * * * Descriptor RAM: 384 bytes I2S bus m...
Description CMOS 32-Bit Microcontroller

File Size 3,123.80K  /  540 Page

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    CS5954AM

CYPRESS[Cypress Semiconductor]
Part No. CS5954AM
OCR Text .................... 11 4.6 USB endpoint 0 Control and Status Register (0xC090: R/W) 4.7 USB endpoint 1 Control and Status Register (0xC092: R/W) 4.8 USB endpoint 2 Control and Status Register (0xC094: R/W) 4.9 USB endpoint 3 Control and St...
Description USB Controller for NAND Flash

File Size 408.62K  /  44 Page

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    CS8818

List of Unclassifed Manufacturers
N.A.
ETC
Part No. CS8818
OCR Text ...RAM buffer and the size of each endpoint is configurable - Default control endpoints (EP0) with up to 64-byte buffer on either TX or RX direction - An interrupt OUT endpoint (EP1) and an interrupt IN endpoint (EP2) - A bulk OUT endpoint (EP...
Description General Purpose USB2.0-to-ATAPI Bridge Controller With Embedded PHY

File Size 105.90K  /  2 Page

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    TMP92CF26AXBG

Toshiba Semiconductor
Part No. TMP92CF26AXBG
OCR Text ...) (Low-speed is not supported.) endpoint 0: Control 64 bytes x 1 FIFO endpoint 1: BULK (output) 64 bytes x 2 FIFOs endpoint 2: BULK (input) 64 bytes x 2 FIFOs endpoint 3: Interrupt (input) 8 bytes x 1 FIFO * * * * * * * * * * * Descriptor R...
Description Original CMOS 32-Bit Microcontroller

File Size 5,000.21K  /  767 Page

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    AT89C5130A-M

ATMEL Corporation
Part No. AT89C5130A-M
OCR Text ...errupt on transfer completion ? endpoint 0 for control transfers: 32-byte fifo ? 6 programmable endpoints with in or out directions and with bulk, interrupt or isochronous transfers endpoint 1, 2, 3: 32-byte fifo endpoint 4, 5: 2 x 64-byt...
Description (AT89C5130A-M / AT89C5131A-M) 8-bit Flash Microcontroller

File Size 1,397.96K  /  186 Page

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    M66291HP

Renesas Electronics Corporation
Part No. M66291HP
OCR Text ...set 7 endpoints (maximum). Each endpoint can be set programmable of its transfer condition, so can correspond to each device class transfer system of USB. 1.1 Features USB Specification Revision 2.0 compliant Supports Full Speed (12 Mbp...
Description ASSP (USB2.0 Device Controller)

File Size 910.75K  /  126 Page

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    PEX8648-AARDK PEX8648-AA50BCG PEX8648

PLX Technology
Part No. PEX8648-AARDK PEX8648-AA50BCG PEX8648
OCR Text ...g the processor subsystem as an endpoint rather than another memory system. Base address registers are used to translate addresses; doorbell registers are used to send interrupts between the address domains; and scratchpad registers (access...
Description PCIe Gen2, 5.0GT/s 48-lane, 12-port PCIe Switch

File Size 228.79K  /  4 Page

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    PEX8632-AARDK PEX8632-AA50BCG PEX8632

PLX Technology
Part No. PEX8632-AARDK PEX8632-AA50BCG PEX8632
OCR Text ...g the processor subsystem as an endpoint rather than another memory system. Base Secondary Secondary address registers are used to Primary Primary Host Host Host Host translate addresses; doorbell CPU CPU registers are used to send Blade Bl...
Description PCIe Gen2, 5.0GT/s 32-lane, 12-port Switch

File Size 201.35K  /  4 Page

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For endpoint Found Datasheets File :: 1555    Search Time::1.219ms    
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