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IDT
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Part No. |
IDTQS74FCT2157CT IDTQS74FCT2157AT
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OCR Text |
... NOUS CONTROL PRESET CLEAR ETC. synchron OUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
FCTL link
LOW -HIGH-LOW PULSE tW HIG H-LOW -HIGH PULSE
FCTL link
1.5V
1.5V
tSU
tH
... |
Description |
HIGH-SPEED CMOS QUAD 2-INPUT MULTIPLEXER
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File Size |
59.06K /
6 Page |
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it Online |
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Cypress Semiconductor, Corp.
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Part No. |
CY7C1277V18-300BZC CY7C1266V18-300BZXC CY7C1266V18-333BZC CY7C1266V18-333BZXC
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OCR Text |
...ites are conducted with on-chip synchron ous self-timed write circuitry. selection guide description 400 mhz 375 mhz 333 mhz 300 mhz unit maximum operating frequency 400 375 333 300 mhz maximum operating current 1280 1210 1080 1000 ma note... |
Description |
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4M X 9 DDR SRAM, 0.45 ns, PBGA165 36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4M X 8 DDR SRAM, 0.45 ns, PBGA165
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File Size |
449.61K /
27 Page |
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it Online |
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NXP Semiconductors N.V.
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Part No. |
DAC1008D650HN DAC1008D6501012
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OCR Text |
...3.125 gbps. the multiple device synchron ization (mds) guarantees a maximum skew of one output clock period between several dac devices. md s incorporates modes: master/slave and all slave mode. 2. features and benefits dac1008d650 dua... |
Description |
Dual 10-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating 10-BIT DAC, PQCC64 Dual 10-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface
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File Size |
524.08K /
98 Page |
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it Online |
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Altera, Corp.
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Part No. |
EP20K400E
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OCR Text |
...s serially or in parallel, and synchron ously or asynchronously. the interface also enables microprocessors to trea t apex 20k devices as memory and configure the device by writing to a virtual memory location, making reconfiguration e... |
Description |
Programmable Logic Device Family 可编程逻辑器件系列
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File Size |
593.38K /
117 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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