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EDB101 D2011 1502A MIP0223 MA43002 C141C 28F320 C1942
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For synchron Found Datasheets File :: 248    Search Time::1.109ms    
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    CY7C1373D-100AXC CY7C1373D-133BZI CY7C1371D-133BGC CY7C1371D-133AXC CY7C1371D-100AXI CY7C1371D-100AXC

Cypress Semiconductor
Part No. CY7C1373D-100AXC CY7C1373D-133BZI CY7C1371D-133BGC CY7C1371D-133AXC CY7C1371D-100AXI CY7C1371D-100AXC
OCR Text ...ites are conducted with on-chip synchron ous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tristate cont rol. to avoid bus...
Description 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL Architecture

File Size 841.63K  /  37 Page

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    DAC1208D650 DAC1208D650HN

Integrated Device Technology
Part No. DAC1208D650 DAC1208D650HN
OCR Text ...3.125 gbps. the multiple device synchron ization (mds) guarantees maximum skew of one output clock period between several dac devices. md s incorporates modes: master/slave and all slave mode. 2. features and benefits dac1208d650 dual ...
Description Dual 12-bit DAC; up to 650 Msps; 2? 4?or 8?interpolating with JESD204A interface

File Size 574.11K  /  96 Page

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    CY7C1372DV25-167AXC

Cypress Semiconductor
Part No. CY7C1372DV25-167AXC
OCR Text ...ites are conducted with on-chip synchron ous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output three-state control. in order t...
Description 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL Architecture

File Size 566.72K  /  30 Page

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    LC89052TA-E

Sanyo Semicon Device
Part No. LC89052TA-E
OCR Text ...rates a built-in pll circuit to synchron ize with transferred bi -phase mark signal. ? can receive input with sampling fr equencies of 32khz to 192khz. ? can set the upper limit of samp ling frequency of received data. ? can receive ...
Description Digital Audio Interface Receiver

File Size 229.82K  /  42 Page

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    CY7C2665KV18 CY7C2663KV18

Cypress Semiconductor
Part No. CY7C2665KV18 CY7C2663KV18
OCR Text ...ites are conducted with on-chip synchron ous self-timed write circuitry. selection guide description 550 mhz 450 mhz unit maximum operating frequency 550 450 mhz maximum operating current 18 1090 940 ma 36 1520 1290 note 1. the cypress ...
Description 144-Mbit QDR? II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

File Size 619.29K  /  31 Page

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    IDT
Part No. IDTQS74FCT2157CT IDTQS74FCT2157AT
OCR Text ... NOUS CONTROL PRESET CLEAR ETC. synchron OUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tH 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V FCTL link LOW -HIGH-LOW PULSE tW HIG H-LOW -HIGH PULSE FCTL link 1.5V 1.5V tSU tH ...
Description HIGH-SPEED CMOS QUAD 2-INPUT MULTIPLEXER

File Size 59.06K  /  6 Page

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    20XS4200 MC20XS4200

Freescale Semiconductor, Inc
Part No. 20XS4200 MC20XS4200
OCR Text ...he external micro-processor to synchron ize to the device when operating in autonomous operating mode. sync is open-drain and requires a pull-up resistor to vdd. table 1. 20xs4200 pin description (continued) the function of each pin is ...
Description Dual 24 V, 20 mOhm High Side Switch

File Size 753.01K  /  60 Page

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    Cypress Semiconductor, Corp.
Part No. CY7C1277V18-300BZC CY7C1266V18-300BZXC CY7C1266V18-333BZC CY7C1266V18-333BZXC
OCR Text ...ites are conducted with on-chip synchron ous self-timed write circuitry. selection guide description 400 mhz 375 mhz 333 mhz 300 mhz unit maximum operating frequency 400 375 333 300 mhz maximum operating current 1280 1210 1080 1000 ma note...
Description 36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4M X 9 DDR SRAM, 0.45 ns, PBGA165
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4M X 8 DDR SRAM, 0.45 ns, PBGA165

File Size 449.61K  /  27 Page

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    NXP Semiconductors N.V.
Part No. DAC1008D650HN DAC1008D6501012
OCR Text ...3.125 gbps. the multiple device synchron ization (mds) guarantees a maximum skew of one output clock period between several dac devices. md s incorporates modes: master/slave and all slave mode. 2. features and benefits dac1008d650 dua...
Description Dual 10-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating 10-BIT DAC, PQCC64
Dual 10-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

File Size 524.08K  /  98 Page

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    Altera, Corp.
Part No. EP20K400E
OCR Text ...s serially or in parallel, and synchron ously or asynchronously. the interface also enables microprocessors to trea t apex 20k devices as memory and configure the device by writing to a virtual memory location, making reconfiguration e...
Description Programmable Logic Device Family 可编程逻辑器件系列

File Size 593.38K  /  117 Page

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