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  dual-cpu Datasheet PDF File

For dual-cpu Found Datasheets File :: 9307    Search Time::3.578ms    
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    SCN2681T SCN2681TC1A44 SCN2681TC1N40 SCN2681T_2

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. SCN2681T SCN2681TC1A44 SCN2681TC1N40 SCN2681T_2
OCR Text Dual asynchronous receiver/transmitter (DUART) Product specification Supersedes data of 1995 May 01 IC19 Data Handbook 1998 Sep 04 Phili...CPU wait states * Dual full-duplex asynchronous receiver/transmitters * Quadruple buffered receiver ...
Description From old datasheet system
Dual asynchronous receiver/transmitter DUART

File Size 114.55K  /  14 Page

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    SCN2681 SCN2681AC1A44 SCN2681AC1N24 SCN2681AC1N28 SCN2681AC1N40 SCN2681AE1A44 SCN2681AE1N24 SCN2681AE1N28 SCN2681AE1N40

PHILIPS[Philips Semiconductors]
Part No. SCN2681 SCN2681AC1A44 SCN2681AC1N24 SCN2681AC1N28 SCN2681AC1N40 SCN2681AE1A44 SCN2681AE1N24 SCN2681AE1N28 SCN2681AE1N40
OCR Text Dual asynchronous receiver/transmitter (DUART) Product specification Supersedes data of 1995 May 01 IC19 Data Handbook 1998 Sep 04 Phili...CPU. D0 is the least significant bit. Chip Enable: Active-Low input signal. When Low, data transfers...
Description Dual asynchronous receiver/transmitter DUART

File Size 205.20K  /  30 Page

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    Fujitsu Microelectronics
Part No. MB89P637-SH MB89T635P-SH MB89635P-SH MB89T637P-SH MB89637P-SH MB89636P-SH MB89635PF MB89637PFM MB89635PFM MB89636PFM MB89P637PF MB89T635PF
OCR Text ...of peripheral functions such as dual-clock control system, five operating speed control stages, a UART, timers, a PWM timer, a serial interf...CPU core Multiplication and division instructions 16-bit arithmetic operations Test and branch instr...
Description 8-bit Proprietary Microcontroller

File Size 411.65K  /  56 Page

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    Broadcom
Part No. BCM1280
OCR Text dual-core 64-bit mips ? processor with spi-4/ht (new!) ? two 64-bit mips ? cpus, scalable from 800 mhz?1.2 ghz  quad issue in-order pipel...cpu core frequency and is 256 bits wide  on-chip l2 cache  1 mb shared by two cpus and i/o agents ...
Description Dual-Core 64-bit MIPS® Processor with SPI-4/HT

File Size 112.30K  /  2 Page

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    INTEGRATED DEVICE TECHNOLOGY INC
Part No. IDT79RC32V334-100BB8 IDT79RC32V334-100BBGI
OCR Text ...ces ? supports flash rom, sram, dual-port memory, and peripheral devices ? supports external wait-state generation ? 8-bit boot prom suppor...cpu rc5000 compatible cp0 32-page tlb ejtag in-circuit emulator interface 2kb 2-set, lockable data c...
Description 32-BIT, 100 MHz, RISC MICROCONTROLLER, PBGA256

File Size 323.75K  /  30 Page

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    飞思卡尔半导体(中国)有限公司
Part No. MCF5270
OCR Text ... or split i-/d-cache ? 64-kbyte dual-ported sram on cpu internal bus, accessible by core and non-core bus masters (e.g., dma, fec) ? fast ethernet controller (fec) ? 10 baset capability, half duplex or full duplex ? 100 baset capability, ...
Description 32-bit Embedded Controller Division 32位嵌入式控制器部

File Size 1,096.39K  /  56 Page

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    IBR-I3-R-3217UE IBR-I7-R-3555LE

List of Unclassifed Manufacturers
List of Unclassifed Man...
Part No. IBR-I3-R-3217UE IBR-I7-R-3555LE
OCR Text dual core 3rd generation intel ? core? processor mobile intel ? qm77 express chipset up to 16gb ecc 1600mhz ddr3 memory in two sodi...cpu 3rd generation intel ? core? i7/i3, 22nm process, bga type intel ? core? i7-3615qe 2.3ghz ...
Description Extreme Rugged COM Express? Type 6 Module with 3rd Generation Intel? Core i3/i7 Processor
Extreme Rugged?COM Express? Type 6 Module with 3rd Generation Intel? Core?i3/i7 Processor

File Size 464.70K  /  3 Page

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    CS51312GD16 CS51312GDR16 CS51312

CHERRY[Cherry Semiconductor Corporation]
Part No. CS51312GD16 CS51312GDR16 CS51312
OCR Text dual NFET Buck Regulator Controller. It is designed to power the core logic of the latest high performance CPUs and ASICs from a single 12V ...CPU and Power system. The CS51312 provides the industry's most highly integrated solution, minimizin...
Description Synchronous CPU Buck Controller for 12V Only Applications

File Size 274.10K  /  18 Page

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    Broadcom
Part No. BCM1480
OCR Text ...ad-issue in-order pipeline with dual-execute and dual- memory pipes  enhanced skew pipeline enables a zero load-to-use penalty  32-kb inst...cpu core frequency and is 256 bits wide  on-chip l2 cache  1 mb shared by four cpus and i/o agents...
Description Quad-Core 64-bit MIPS® Processor with SPI-4/HT

File Size 115.94K  /  2 Page

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