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Motorola
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| Part No. |
MPC9850
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| OCR Text |
...* * * * * * * * *
Features 8 lvcmos outputs for processor and other circuitry 2 differential lvds outputs for Rapid I/O interface Crystal oscillator or external reference input 25 or 33 MHz Input reference frequency Selectable output fre... |
| Description |
Clock Generator for PowerQULCC III
From old datasheet system
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| File Size |
152.76K /
12 Page |
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it Online |
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ICS
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| Part No. |
ICS8737-11
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| OCR Text |
... any single ended input signal (lvcmos, LVTTL, GTL) to lvpecl levels with resistor bias on nCLK input * Output skew: 60ps (maximum) * Part-t...lvds, lvpecl, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the V... |
| Description |
Low Skew, ÷1, ÷2 Clock Generator
From old datasheet system
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| File Size |
203.80K /
16 Page |
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it Online |
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ICS
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| Part No. |
ICS8737I-11 ICS8737-11I
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| OCR Text |
... any single ended input signal (lvcmos, LVTTL, GTL) to lvpecl levels with resistor bias on nCLK input * Output skew: 75ps (maximum) * Part-to-part skew: 300ps (maximum) * Bank skew: Bank A - 30ps (maximum) Bank B - 45ps (maximum) * 3.3V ope... |
| Description |
Low Skew, ÷1, ÷2 Clock Generator. Industrial Temperature.
From old datasheet system
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| File Size |
98.98K /
14 Page |
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it Online |
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Actel
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| Part No. |
A3P1000
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| OCR Text |
...gle-Ended I/O Standards: LVTTL, lvcmos 3.3 V/ 2.5 V/ 1.8 V/1.5 V, 3.3 V PCI/3.3 V PCI-X (except A3P030), and lvcmos 2.5 V/5.0 V Input Differential I/O Standards: lvpecl and lvds (A3P250 and above) I/O Registers on Input, Output, and Enable ... |
| Description |
ARM7TM Soft IP Support in ProASIC3 ARM7-Ready Devices
From old datasheet system
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| File Size |
1,181.46K /
186 Page |
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it Online |
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ICS
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| Part No. |
ICS874003
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| OCR Text |
...rs and the outputs are enabled. lvcmos/LVTTL interface levels. Pullup/ Selects PLL Band Width input. lvcmos/LVTTL interface levels. Pulldown...lvds interface levels.
6 7 8 9 10 11 12 13 14 15 16 17, 18
BW_SEL nc VDDA F_SELA VDD OEA CLK n... |
| Description |
High Performance Differential-to-lvds Jitter Attenuator for PCI Express?
From old datasheet system
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| File Size |
185.07K /
10 Page |
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it Online |
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ONSEMI[ON Semiconductor]
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| Part No. |
NB6L11 NB6L11DTR2 NB6L11D NB6L11DR2 NB6L11DT
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| OCR Text |
...t accept LVNECL, lvpecl, LVTTL, lvcmos, CML, or lvds. The outputs are 800 mV ECL signals. * Maximum Input Clock Frequency w 6 GHz Typical * Maximum Input Data Rate w 6 Gb/s Typical * Low 14 mA Typical Power Supply Current * 150 ps Typical P... |
| Description |
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL lvpecl/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR 6L SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
6GHz 2.5V/3.3V Multilevel Input to Differential LVNECL/lvpecl 1:2 Clock or Data Fanout Buffer/Transl
From old datasheet system
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| File Size |
112.11K /
12 Page |
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it Online |
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on
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| Part No. |
NB6L16
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| OCR Text |
..., lvpecl (Positive ECL), LVTTL, lvcmos, CML, or lvds. Outputs are 800 mV ECL signals. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is... |
| Description |
6GHz/6Gbps 2.5V/3.3V Multi-level Input to Differential LVECL Clock or Data Translator/Receiver/Drive
From old datasheet system
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| File Size |
112.87K /
12 Page |
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it Online |
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