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pecl cmos Datasheet PDF File

For pecl cmos Found Datasheets File :: 1362 Search Time::2.469ms
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				ATMEL Corporation
Part No.	ATC18RHA
OCR Text	... LVpecl Buffer The PE33RXZ pecl buffer is a simplified version of PL33RXZ LVDS buffer. It is a differential input with LVpecl levels and it does not need Ref. So it can be implemented inside a standard IO33 cluster. The pecl RX occupie...
Description	Rad. Hard 0.18 Um cmos Cell-based ASIC for Space Use
File Size	217.03K / 19 Page	View it Online	Download Datasheet

				STMicroelectronics
Part No.	ISB35000 ISB35083 ISB35130 ISB35166
OCR Text	...y including LVcmos, LVTTL, GTL, pecl, and LVDS. High drive I/O; capability of sinking up to 48 mA with slew rate control, current spike supp...cmos and TTL to 200 mHz plus low swing differential circuits. Standards like GTL, SCSI-2, 3.3 Volt P...
Description	Hcmos STRUCTURED ARRAY
File Size	276.47K / 15 Page	View it Online	Download Datasheet

				ETC
Part No.	TC-210 TC-210-CAB-307A TC-210-CAB-ST3A TC-210-CAC-507A TC-210-CAC-ST3A TC-210-CAF-106A TC-210-CBB-307A TC-210-CBB-ST3A TC-210-CBC-507A TC-210-CBC-ST3A TC-210-CBF-106A TC-210-CFB-307A TC-210-CFB-ST3A TC-210-CFC-507A TC-210-CFC-ST3A TC-210-CFF-106A TC-210-CGB-307A TC-210-CGB-ST3A TC-210-CGC-507A TC-210-CGC-ST3A TC-210-CGF-106A TC-210-DAB-307A TC-210-DAB-ST3A TC-210-DAC-507A TC-210-DAC-ST3A TC-210-DAF-106A TC-210-DBB-307A TC-210-DBB-ST3A TC-210-DBC-507A TC-210-DBC-ST3A
OCR Text	... outputs available (TTL, Hcmos, pecl, SINEWAVE) Stratum 3 Applications SONET/SDH Network Timing Sources DWDM / FDM / ATM Wireless Communi...cmos (A) (G) pecl (F) TC- 210 - X X X - X X X A Supply Voltage C = 5 Vdc +/-5% D = 3.3 Vdc...
Description	TEMPERATURE COMPENSATED CRYSTAL OSCILLATORS
File Size	382.67K / 5 Page	View it Online	Download Datasheet

				Motorola
Part No.	MPC9456
OCR Text	... The clock input is low voltage pecl compatible for differential clock distribution support. Please consult the MPC9446 specification for a full cmos compatible device. For series terminated transmission lines, each of the MPC9456 outputs c...
Description	MPC9456 2.5V and 3.3V LVcmos Clock Fanout Buffer 2.5V and 3.3V LVcmos Clock Fanout Buffer
File Size	133.67K / 12 Page	View it Online	Download Datasheet

				OKI electronic components OKI[OKI electronic componets]
Part No.	MSM13Q MSM14Q000 MSM13Q000 MSM13Q0000 MSM14Q1020 MSM13Q0150 MSM13Q0230 MSM13Q0340 MSM13Q0530 MSM13Q0840 MSM13Q1020 MSM14Q0000 MSM14Q0150 MSM14Q0230 MSM14Q0340 MSM14Q0530 MSM14Q0840
OCR Text	..., pseudo-emitter coupled logic (pecl), peripheral component interconnect (PCI), universal synchronous receiver/transmitter (UART) cells, and...cmos * Optimized 3.3-V core * Optimized 3-V I/O and 3-V I/O that is 5-V tolerant * CBA SOG architect...
Description	0.35 m Sea of Gates Arrays 0.35 レm Sea of Gates Arrays
File Size	118.52K / 20 Page	View it Online	Download Datasheet

				NXP Semiconductors N.V. Philips Semiconductors
Part No.	TDA9901 TDA9901TS TDA9901_2 TDA9901TS/C3118
OCR Text	...r differential clock input with pecl compatibility * 24 dB gain control range * Five steps of 6 dB plus 6 dB fixed gain * 30 dB gain maximum * High impedance differential inputs * Low impedance differential outputs * High power supply rejec...
Description	Wideband differential digital controlled variable gain amplifier; Package: SOT266-1 (SSOP20); Container: Reel Pack, SMD, 13" SPECIALTY ANALOG CIRCUIT, PDSO20 From old datasheet system
File Size	92.75K / 20 Page	View it Online	Download Datasheet

				Agilent(Hewlett-Packard)
Part No.	HDMP-0421
OCR Text	...zers On All Inputs * High Speed pecl I/Os Referenced to VCC * Buffered Line Logic (BLL) Outputs without External Bias Resistors * 0.4 W Typi...cmos ASIC to clean the jitter of the outgoing signal (CDR path) and to better read the incoming sign...
Description	Port Bypass Circuits for Fibre Channel Arbitrated Loop Standard and its Extensions
File Size	151.46K / 12 Page	View it Online	Download Datasheet

				Integrated Circuit Systems
Part No.	ICS1523
OCR Text	...DPA) for clock outputs Balanced pecl differential outputs Single-ended SSTL_3 clock outputs Double-buffered PLL/DPA control registers Indepe...cmos rail-to-rail logic or as a terminated transmission line system at higher-output frequencies. Wi...
Description	High-Performance Programmable Line-Locked Clock Generator
File Size	941.24K / 27 Page	View it Online	Download Datasheet

				Samsung semiconductor
Part No.	KM718FV4021
OCR Text	...nd Output Levels. Differential, pecl Clock Inputs K, K. Synchronous Read and Write Operation Registered Input and Registered Output Internal...cmos technology. Single differential pecl level K clocks are used to initiate the read/write operati...
Description	128Kx36 & 256Kx18 Synchronous Pipelined SRAM
File Size	235.93K / 12 Page	View it Online	Download Datasheet

For pecl cmos Found Datasheets File :: 1362 Search Time::2.469ms
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