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    HYB18H256321BF HYB18H256321BF-11_12_14

Qimonda AG
Part No. HYB18H256321BF HYB18H256321BF-11_12_14
OCR Text ...be (WDQS) per byte. WDQS center-aligned with WRITE data * DLL aligns RDQS and DQ transitions with Clock * Programmable IO interface including on chip termination (ODT) * Autoprecharge option with concurrent auto precharge support * 4k Refre...
Description 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM

File Size 1,336.70K  /  41 Page

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    RMLD232UAW-7E

Emerging Memory & Logic Solutions Inc
Part No. RMLD232UAW-7E
OCR Text ...ta strobe, DM for masking. Edge aligned data output, center aligned data input. No DLL; CK to DQS is not synchronized. DM0 - DM3 for write masking only. 15.6 auto refresh duty cycle. Opreating Frequency DDR266 Speed @CL...
Description 2M x 32 bit Low Power DDR SDRAM

File Size 2,208.71K  /  50 Page

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Part No. MT8VDDT1664AG-403A1
OCR Text ...ach positive ck edge  dqs edge-aligned with data for reads; center- aligned with data for writes  internal, pipelined double data rate (ddr) architec- ture; two data accesses per clock cycle  bidirectional data strobe (dqs) transmitted/ ...
Description 16M X 64 DDR DRAM MODULE, 0.6 ns, DMA184

File Size 335.96K  /  16 Page

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    HYB18M1G16 HYB18M1G160BF-7.5 HYE18M1G161BF-7.5 HYE18M1G160BF-7.5 HYB18M1G161BF-7.5 HYE18M1G160BF-6 HYE18M1G161BF-6

Qimonda AG
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Part No. HYB18M1G16 HYB18M1G160BF-7.5 HYE18M1G161BF-7.5 HYE18M1G160BF-7.5 HYB18M1G161BF-7.5 HYE18M1G160BF-6 HYE18M1G161BF-6
OCR Text ...ata at the receiver DQS is edge-aligned with data for READs and center-aligned with data for WRITEs Differential clock input (CK / CK) Commands entered on positive CK edge; data and mask data are referenced to both edges of DQS Four interna...
Description 1-Gbit x16 DDR Mobile-RAM 64M X 16 DDR DRAM, 5.5 ns, PBGA60

File Size 2,428.42K  /  65 Page

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    HYB18M1G320BF HYE18M1G320BF-7.5 HYB18M1G320BF-7.5

Qimonda AG
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Part No. HYB18M1G320BF HYE18M1G320BF-7.5 HYB18M1G320BF-7.5
OCR Text ...ata at the receiver DQS is edge-aligned with data for READs and center-aligned with data for WRITEs Differential clock input (CK / CK) Commands entered on positive CK edge; data and mask data are referenced to both edges of DQS Four interna...
Description DRAMs for Mobile Applications 1-Gbit x32 DDR Mobile-RAM 8M X 32 DDR DRAM, 6.5 ns, PBGA90

File Size 2,409.33K  /  62 Page

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    MC68HC912BL16 MC68HC912BL16CFU8 MC68HC912BL16FU8 MC68HC912BL16MFU8 MC68HC912BL16VFU8

Freescale Semiconductor, Inc
Part No. MC68HC912BL16 MC68HC912BL16CFU8 MC68HC912BL16FU8 MC68HC912BL16MFU8 MC68HC912BL16VFU8
OCR Text ...AM with Single-Cycle Access for aligned or Misaligned Read/Write * 8-Channel, 10-bit Analog-to-Digital Converter * 7-Channel Timer -- Each Channel Fully Configurable as Either Input Capture or Output Compare -- Simple PWM Mode -- Modulo Res...
Description 16-Bit Microcontroller

File Size 1,106.92K  /  128 Page

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    CY230308

Cypress Semiconductor
Part No. CY230308
OCR Text aligned Clock Multiplier Features Functional Description The CY2303 is a 3 output 3.3V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance appli...
Description Phase-aligned Clock Multiplier

File Size 174.62K  /  7 Page

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    FS6131-01G FS6131-01I-XTD FS6131-01G-XTD FS613108

Rectron Semiconductor
Part No. FS6131-01G FS6131-01I-XTD FS6131-01G-XTD FS613108
OCR Text ...the VCO output is exactly phase aligned with the input clock. Every cycle of the input clock equals NR/NF cycles of the VCO clock. fIN Reference Divider (NR) Phase Frequency Detect VCO fOUT fIN fOUT Feedback Divider (NF...
Description Programmable Line Lock Clock Generator IC

File Size 498.11K  /  44 Page

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    HYB25D256160CC-5 HYB25D256160CC-6 HYI25D256160CC-6 HYB25D256160CE-5 HYB25D256800CE-5 HYB25D256800CTL-6 HYB25D256800CE-5A

Qimonda AG
Part No. HYB25D256160CC-5 HYB25D256160CC-6 HYI25D256160CC-6 HYB25D256160CE-5 HYB25D256800CE-5 HYB25D256800CTL-6 HYB25D256800CE-5A HYB25D256160CE-5A HYI25D256800CE-5 HYB25D256800CF-5 HYI25D256800CF-5 HYB25D256800CF-6
OCR Text ...a at the receiver * DQS is edge-aligned with data for reads and is centeraligned with data for writes * Differential clock inputs (CK and CK) * Four internal banks for concurrent operation * Data mask (DM) for write data * DLL aligns DQ and...
Description 256-Mbit Double-Data-Rate SDRAM
   256-Mbit Double-Data-Rate SDRAM

File Size 1,077.84K  /  39 Page

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    NANYA TECHNOLOGY CORP
Part No. NT5DS64M8AF-6K
OCR Text ... at the receiver  dqs is edge-aligned with data for reads and is center- aligned with data for writes  differential clock inputs (ck and ck )  four internal banks for concurrent operation  data mask (dm) for write data  dll aligns dq ...
Description 64M X 8 DDR DRAM, 0.7 ns, PBGA60

File Size 2,293.16K  /  76 Page

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ALIGNMENT-DISC-APD-37-WAY
ITT Interconnect Solutions Alignment disc for 37-way Flange Receptacle 10000: USD0.82
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