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Cypress Semiconductor Corp.
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| Part No. |
CY7C372I
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| OCR Text |
... On the other hand, in CPLD and FPGA architectures without simple and predictable timing, PCI compliance is dependent upon routing and product term distribution. 3.3V or 5.0V I/O operation The FLASH370i family can be configured to operate i... |
| Description |
UltraLogic 64-Macrocell Flash CPLD(超逻辑4 宏单闪CPLD)
From old datasheet system
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| File Size |
157.52K /
11 Page |
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it Online |
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MAXIM[Maxim Integrated Products]
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| Part No. |
DS4520 DS4520E
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| OCR Text |
...4520
Applications
RAM-Based FPGA Bank Switching for Multiple Profiles Selecting Between Boot Flash Setting ASIC Configurations/Profiles ...40 -20 0 20 40 60 80 TEMPERATURE (C)
SUPPLY CURRENT vs. SCL FREQUENCY
DS4520 toc03
I/O OUTPUT... |
| Description |
From old datasheet system
9-Bit I2C Nonvolatile I/O Expander Plus Memory
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| File Size |
955.79K /
10 Page |
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it Online |
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quicklogic
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| Part No. |
QL5432 QL5432_DS
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| OCR Text |
...s * Has 125 more logic cells in FPGA section, but 2 less RAM blocks * Pin compatible with QL5232 QL5432 also supports the original features ...40 wide) * 1 FIFO at 215 deep (40 wide)
(c) 2004 QuickLogic Corporation
www.quicklogic.com * *... |
| Description |
33 MHz/32-Bit PCI Master/Target with Embedded
Programmable Logic and Dual Port SRAM
From old datasheet system
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| File Size |
716.33K /
27 Page |
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it Online |
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pmc
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| Part No. |
2001398
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| OCR Text |
...ics
SONET Line/ Section
I/F FPGA
UL3/ PL3 32-Bit Master
S/UNI-2xGE
PL3 SLAVE LAYER 2 GMAC CRU/CSU
UL3 /PL3 SLAVE
EOS Function FIFO
UL3/ PL3 32-Bit Master
SFF Optics
SFF Optics
APS
RAM I/F
OPTIONAL RAM
RMON
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| Description |
From old datasheet system
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| File Size |
177.63K /
19 Page |
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it Online |
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Price and Availability
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