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Integrated Device Techn...
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| Part No. |
8S89833 8S89833AKILF 8S89833AKILFT 8S89833-17
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| OCR Text |
...eatures four differential lvds outputs in, nin input pair can accept the fo llowing differential input levels: lvpecl, lvds, cml output frequency: 2ghz cycle-to-cycle jitter, rms: 3.5ps (maximum) additive phase jitter, rms: 0.03ps (t... |
| Description |
Low Skew, 1-To-4 Different ial-To-LVDS Fanout Buffer w/Internal Terminat ion
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| File Size |
318.58K /
15 Page |
 View
it Online |
Download Datasheet
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Integrated Device Techn...
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| Part No. |
8S89833AKILF
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| OCR Text |
...atures ? four differential lvds outputs ? in, nin input pair can accept the fo llowing differential input levels: lvpecl, lvds, cml ? output frequency: 2ghz ? cycle-to-cycle jitter, rms: 3.5ps (maximum) ? additive phase jitter, rms: 0.03p... |
| Description |
Low Skew, 1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination
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| File Size |
312.23K /
17 Page |
View
it Online |
Download Datasheet |
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Integrated Device Techn...
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| Part No. |
8S89832AKILF 8S89832AKILFT 8S89832I
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| OCR Text |
...zing clock enable. when low, qx outputs will go low and nqx outputs will go high on the next low transition at in inputs. input threshold is v dd /2v. includes a 37k ? pullup resistor. default state is high wh en left floating. the inter... |
| Description |
Low Skew, 1-to-4 Differential-to-LVDS Fanout Buffer
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| File Size |
289.93K /
16 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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