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INTEGRATED DEVICE TECHNOLOGY INC
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Part No. |
ICSSSTVA32852 ICSSSTVA32852YHLF-T
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OCR Text |
...c state because VREF may not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic "Low" level during power up. In the DDR DIMM application, RE... |
Description |
SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA114 From old datasheet system
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File Size |
118.16K /
7 Page |
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