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Integrated Device Techn...
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| Part No. |
9FGV0831CKLF
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| OCR Text |
...res ? 8 - 100mhz low-power (lp) hcsl dif pair ? 1 - 1.8v lvcmos ref output w/wake-on-lan (wol) support key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-2-3 compliant ? r... |
| Description |
8-O/P 1.8V PCIe Gen 1/2/3 Clock Generator
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| File Size |
334.37K /
17 Page |
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it Online |
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Pericom Semiconductor C...
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| Part No. |
PI6LC4820ZDE
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| OCR Text |
...ential (accepts: lvds, lvpecl, hcsl) 47 in+ input (diferential) frequency input pin, diferential (accepts: lvds, lvpecl, hcsl) 48 in_se in...lvcmos input electrical characteristics symbol parameters conditions min. ty p. max. units v ih inp... |
| Description |
HiFlex Ethernet Network Clock Generator
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| File Size |
939.96K /
13 Page |
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it Online |
Download Datasheet |
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Silicon Laboratories
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| Part No. |
SI5344-D-EVB SI5342B-D-GM SI5344C-D-GM SI5342C-D-GM SI5345B-D-GM
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| OCR Text |
... lvds, lvpecl, lvcmos, cml, and hcsl with programmable signal amplitude ? si5345: 4 input, 10 output, 64-qfn 99 mm ? si5344: 4 input, 4 output, 44-qfn 77 mm ? si5342: 4 input, 2 output, 44-qfn 77 mm up to 10 output clocks si5344 si5345 i2c... |
| Description |
10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier
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| File Size |
1,141.77K /
60 Page |
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it Online |
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Silicon Laboratories
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| Part No. |
SI5341
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| OCR Text |
... lvds, lvpecl, lvcmos, cml, and hcsl with programmable signal amplitude ? si5341: 4 input, 10 output, 64-qfn 9x9 mm ? si5340: 4 input, 4 output, 44-qfn 7x7 mm up to 10 output clocks out7 out6 out5 out1 out4 out3 out2 out0 si5340 si5341 i2c... |
| Description |
Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator
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| File Size |
5,443.68K /
53 Page |
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it Online |
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Integrated Device Techn...
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| Part No. |
9FGV0631CKLF 9FGV0631CKLFT
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| OCR Text |
...res ? 6 - 100mhz low-power (lp) hcsl dif pairs ? 1 - 1.8v lvcmos ref output w/wake-on-lan (wol) support key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-2-3 compliant ? ... |
| Description |
6-O/P 1.8V PCIe Gen 1-2-3 Clock Generator
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| File Size |
201.33K /
15 Page |
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it Online |
Download Datasheet |
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ICST[Integrated Circuit Systems]
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| Part No. |
ICS85214 ICS85214AG
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| OCR Text |
...vels: LVDS, LVPECL, HSTL, SSTL, hcsl * CLK1 can accept the following input levels: lvcmos or LVTTL * Output frequency up to 700MHz * Translates any single ended input signal to HSTL levels with resistor bias on nCLK0 input * Output skew: 30... |
| Description |
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Low Skew, 1-to-5, Differential-to- HSTL Fanout Buffer. VOHmax=1.4V
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| File Size |
105.82K /
16 Page |
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it Online |
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Integrated Device Technology, Inc.
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| Part No. |
ICS83023AMIT ICS83023AMILF ICS83023AMILFT
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| OCR Text |
...lvds, lvhstl, lvpecl, sstl, and hcsl) and translate into two single-ended lvcmos outputs. the small 8-lead soic footprint makes this device ideal for use in ap- plications with limited board space. features ? two lvcmos / lvttl outputs ? ... |
| Description |
DUAL, 1-TO-1 DIFFERENTIAL-TOlvcmos TRANSLATOR/BUFFER 83023 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
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| File Size |
273.40K /
13 Page |
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it Online |
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ICST[Integrated Circuit Systems]
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| Part No. |
ICS85214I ICS85214AGI ICS85214AGIL ICS85214AGILF
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| OCR Text |
...vels: LVDS, LVPECL, HSTL, SSTL, hcsl * CLK1 can accept the following input levels: lvcmos or LVTTL * Output frequency up to 700MHz * Translates any single ended input signal to HSTL levels with resistor bias on nCLK0 input * Output skew: 40... |
| Description |
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Low Skew, 1-to-5, Differential-to-HSTL Fanout Buffer. VOHmax=1.4V
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| File Size |
174.70K /
15 Page |
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it Online |
Download Datasheet |
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ICS
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| Part No. |
ICS874003
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| OCR Text |
...es: LVPECL, LVDS, LVHSTL, SSTL, hcsl * Output frequency range: 98MHz - 160MHz * Input frequency range: 98MHz - 128MHz * VCO range: 490MHz - ...lvcmos/LVTTL interface levels. Pullup/ Selects PLL Band Width input. lvcmos/LVTTL interface levels. ... |
| Description |
High Performance Differential-to-LVDS Jitter Attenuator for PCI Express?
From old datasheet system
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| File Size |
185.07K /
10 Page |
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it Online |
Download Datasheet |
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Price and Availability
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