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  lvcmos lvds lvpecl Datasheet PDF File

For lvcmos lvds lvpecl Found Datasheets File :: 1486    Search Time::2.641ms    
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    MAX3637 MAX3637ETM

Maxim Integrated Products
Part No. MAX3637 MAX3637ETM
OCR Text ...ne differential outputs and one lvcmos output, divided into three banks. The frequency and output interface of each output bank can be indiv...lvds Outputs: Up to 800MHz Three Individual Output Banks Pin-Programmable Dividers Pin-Programmable ...
Description Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs

File Size 2,454.80K  /  23 Page

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    Pericom Semiconductor C...
Part No. PI6C5922504
OCR Text ... -1.5 v dd -1.3 v dd -1.15 v lvcmos/lvttl dc characteristics (ta = -40 o c to +85 o c, v dd = 2.5v 5% to 3.3v 10%) symbol parameter con...lvds fanout bufer with internal termination 14-0127 4 ac characteristics (t a = -40 o c to +8...
Description 2.5 GHz 1:4 lvds Fanout Buffer with Internal Termination

File Size 724.55K  /  12 Page

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    MAX3638 MAX3638ETM

Maxim Integrated Products
Part No. MAX3638 MAX3638ETM
OCR Text ...ne differential outputs and one lvcmos output, divided into three banks. The frequency and output interface of each output bank can be indiv...lvds Outputs: Up to 800MHz Three Individual Output Banks Pin-Programmable Dividers Pin-Programmable ...
Description Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs

File Size 2,236.07K  /  22 Page

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    Integrated Device Techn...
Part No. 8T49N028
OCR Text ...tten after power-up via i 2 c. lvcmos/lvttl interface levels. 00 = configuration 0 (default) 01 = configuration 1 10 = configuration 2 11 =...lvds interface levels. (bank d) 28, 29 nq6, q6 output differentia l output pair. lvpecl or lvds in...
Description Fourth Generation FemtoClock NG PLL technology

File Size 982.96K  /  36 Page

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    Integrated Device Techn...
Part No. IDT8T49N008I
OCR Text ...tten after power-up via i 2 c. lvcmos/lvttl interface levels. 00 = configuration 0 (default) 01 = configuration 1 10 = configuration 2 11 =...lvds interface levels. 24, 25 nq6, q6 output differential output pa ir. lvpecl or lvds interface lev...
Description Fourth Generation FemtoClock NG PLL technology

File Size 478.65K  /  38 Page

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    Integrated Device Techn...
Part No. IDT8T49N004I
OCR Text ...itten after power-up via i 2 c. lvcmos/lvttl interface levels. 00 = configuration 0 (default) 01 = configuration 1 10 = configuration 2 11 =...lvds interface levels. 22, 23 nq2, q2 output differential output pair. lvpecl or lvds interface leve...
Description Fourth Generation FemtoClock NG PLL technology

File Size 762.11K  /  37 Page

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    SI53307

Silicon Laboratories
Part No. SI53307
OCR Text ...k diagram ? 2 differential or 4 lvcmos outputs ? ultra-low additive jitter: 45 fs rms ? wide frequency range: 1 to 725 mhz ? any-format inpu...lvds, cml, hcsl, lvcmos ? synchronous output enable ? 2:1 input mux with glitchless input clock sw...
Description 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

File Size 1,492.81K  /  30 Page

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    SI53304

Silicon Laboratories
Part No. SI53304
OCR Text ... diagram ? 6 differential or 12 lvcmos outputs ? ultra-low additive jitter: 45 fs rms ? wide frequency range: 1 to 725 mhz ? any-format inpu...lvds, cml, hcsl, lvcmos ? 2:1 mux with hot-swappable inputs ? glitchless input clock switching ? s...
Description 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

File Size 1,871.94K  /  33 Page

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    SI53303

Silicon Laboratories
Part No. SI53303
OCR Text ...diagram ? 10 differential or 20 lvcmos outputs ? ultra-low additive jitter: 100 fs rms ? wide frequency range: 1 to 725 mhz ? any-format in...lvds, cml, hcsl, lvcmos ? synchronous output enable ? output clock division: /1, /2, /4 ? low outpu...
Description DUAL 1:5 LOW JITTER BUFFER/LEVEL TRANSLATOR

File Size 1,626.36K  /  30 Page

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For lvcmos lvds lvpecl Found Datasheets File :: 1486    Search Time::2.641ms    
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