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Philips
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| Part No. |
SC16C654DBIB64
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| OCR Text |
...s a logic 0 (connected to gnd). mcr[7] can override the state of this pin following reset or initialization (see mcr[7]). this pin is not av...2, 16, 33, 47 i clear to send (active low). these inputs are associated with individual uart channe... |
| Description |
SC16C654B/654DB; 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs and infrared (IrDA) encoder/decoder
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| File Size |
222.72K /
50 Page |
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Zarlink Semiconductor Inc.
Zarlink Semiconductor, Inc.
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| Part No. |
ARM60 P60ARM-B P60ARM-IG P60ARM-GP1N
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| OCR Text |
...cessor register transfers (mrc, mcr) 57 4.14 undefined instruction 59 4.15 instruction set examples 60 5.0 memory interface 65 5.1 cycle types 65 5.2 byte addressing 66 5.3 address timing 68 5.4 memory management 68 5.5 locked operation... |
| Description |
Low power, general purpose 32-bit RISC microprocessor 低功耗，通用32位RISC微处理器
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| File Size |
1,328.16K /
120 Page |
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it Online |
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NXP Semiconductors N.V.
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| Part No. |
SC16C550B
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| OCR Text |
...pective modem control register (mcr) bits ( out1 and out2). out1 and out2 are set to inactive the (high) level as a result of master reset, during loopback mode operations, or by clearing bit 2 ( out1) or bit 3 ( out2) of the mcr. out2 35 3... |
| Description |
5V, 3.3V and 2.5V UART with 16-byte FIFOs(6字节FIFO/3.3/2.5V 通用同步收发
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| File Size |
235.26K /
48 Page |
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it Online |
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Philips
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| Part No. |
SC16C2552B
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| OCR Text |
...d, the mf pin is a logic 0 when mcr[3] is set to a logic 1. a logic 1 is the default signal condition that is available following a master r...2: pin description continued symbol pin type description
philips semiconductors sc16c2552b 5 v, 3.... |
| Description |
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
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| File Size |
157.75K /
37 Page |
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it Online |
Download Datasheet |
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Philips
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| Part No. |
SC68C2550B
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| OCR Text |
...hrough the software settings of mcr[3]. op2a/ op2b is a logic 0 when mcr[3] is set to a logic 1. op2a/ op2b is a logic 1 when mcr[3] is set ...2 k w resistor. cd a, cdb 40, 16 i carrier detect (active low). these inputs are associated with in... |
| Description |
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs and Motorola uP interface
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| File Size |
149.74K /
35 Page |
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it Online |
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