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phase-lock-loop Datasheet PDF File

For phase-lock-loop Found Datasheets File :: 7403 Search Time::4.562ms
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				NXP Semiconductors N.V. PHILIPS[Philips Semiconductors]
Part No.	HEF4750VLSI HEF4750V HEF4750VD HEF4750VF
OCR Text	...gle crystal. * High-performance phase comparator low phase noise low spurii. * System operation to > 1 GHz. * Typical 15 MHz input at 10 V...lock feature. * Out-of-lock indication. * Low power dissipation and high noise immunity. APPLICATION...
Description	Frequency synthesizer 频率合成
File Size	164.22K / 17 Page	View it Online	Download Datasheet

				INTEGRATED DEVICE TECHNOLOGY INC Integrated Device Technology, Inc. IDT[Integrated Device Technology]
Part No.	IDT5V2528 IDT5V2528A IDT5V2528APG IDT5V2528APGG IDT5V2528APGGI IDT5V2528APGI IDT5V2528PG IDT5V2528PGG IDT5V2528PGGI IDT5V2528PGI IDT5V2528APGGI8 IDT5V2528PGGI8 IDT5V2528APGI8
OCR Text	PHASE-LOCK LOOP CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: * * * * IDT5V2528/A * * * * * * * Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ 1:10 fanout 3-lev...
Description	2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER 2.5V / 3.3V的锁相环时钟驱动器零延迟缓冲 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER .5V / 3.3V的锁相环时钟驱动器零延迟缓冲
File Size	59.21K / 7 Page	View it Online	Download Datasheet

				IDT[Integrated Device Technology]
Part No.	IDT5V9950 IDT5V9950PFI
OCR Text	...the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull-down). S...
Description	3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK? II JR.
File Size	65.38K / 9 Page	View it Online	Download Datasheet

				IDT[Integrated Device Technology]
Part No.	IDT5V9955 IDT5V9955BFI IDT5V9955BFI8
OCR Text	...when the xbank PLL has achieved phase lock. Furthermore, when xPE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When xPE is held low, all the xbank outputs are synchronized with the negative e...
Description	3.3V Programmable Skew Dual PLL Clock Driver Turboclock II 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
File Size	124.58K / 11 Page	View it Online	Download Datasheet

				IDT[Integrated Device Technology]
Part No.	IDT82V3011 IDT82V3011PV IDT82V3011PV8
OCR Text	...frequency accuracy of 0.025 ppm Phase slope of 5 ns per 125 s Attenuates wander from 2.1 Hz Fast lock mode Provides Time Interval Error (TIE) correction MTIE of 600 ns JTAG boundary scan Holdover status indication Freerun status indication ...
Description	T1/E1/OC3 WAN PLL with Single Input Reference Clock T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT T1/E1/OC3(19.44M) WAN PLL, Single Input Reference. Stratum 4/4E
File Size	365.36K / 30 Page	View it Online	Download Datasheet

				IDT[Integrated Device Technology]
Part No.	IDT82V3012 IDT82V3012PV IDT82V3012PV8
OCR Text	...equency accuracy of 0.025 ppm * Phase slope of 5 ns per 125 s * Attenuates wander from 2.1 Hz * Fast lock mode * Provides Time Interval Error (TIE) correction * MTIE of 600 ns * JTAG boundary scan * Holdover status indication * Freerun stat...
Description	T1/E1/OC3(19.44M) WAN PLL, Dual Input Reference. Stratum 3/4/4E T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
File Size	364.91K / 30 Page	View it Online	Download Datasheet

For phase-lock-loop Found Datasheets File :: 7403 Search Time::4.562ms
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