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EXAR[Exar Corporation]
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Part No. |
XRT8000_06 XRT8000 XRT8000ID XRT8000IP
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OCR Text |
...aneous, very low jitter, output clocks for synchronization applications in wide area networking systems. The outputs are phase locked to the input signal. The chip has four basic modes of operation; referred to as master (FORWARD, REVERSE) ... |
Description |
Clock Synchronizer/Adapter for Communications
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File Size |
624.22K /
24 Page |
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it Online |
Download Datasheet |
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INTEGRATED DEVICE TECHNOLOGY INC
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Part No. |
97ULP877BH ICS97ULP877BHLF
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OCR Text |
...uts are controlled by the input clocks (clk_int, clk_inc), the feedback clocks (fb_int, fb_inc), the lvcmos program pins (oe, os) and the analog power input (avdd). when oe is low, the outputs (except fb_outt/fb_outc) are disabled while the... |
Description |
97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
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File Size |
238.98K /
15 Page |
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it Online |
Download Datasheet |
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Price and Availability
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