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  lvcmos lvds lvpecl Datasheet PDF File

For lvcmos lvds lvpecl Found Datasheets File :: 1484    Search Time::3.187ms    
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    ICS
Part No. ICS87158
OCR Text lvcmos /1, /2, /4 CLOCK GENERATOR FEATURES * 6 HCSL outputs * 2 lvcmos/LVTTL outputs * 1 Differential lvpecl clock input pair * PCLK, nPCLK supports the following input types: lvds, lvpecl, LVHSTL, SSTL, HCSL * Maximum output frequency: 6...
Description Low Skew 1-to-6 ÷1, 2, 4 Clock Generator.
From old datasheet system

File Size 253.44K  /  16 Page

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    ICS
Part No. ICS87159
OCR Text lvcmos outputs * lvpecl clock input pair * PCLK, nPCLK supports the following input types: lvds, lvpecl, LVHSTL, SSTL, HCSL * Maximum output frequency: 600MHz * Output skew: 110ps (maximum) * Propagation delay: 3.6ns (maximum) * 3.3V operat...
Description Low Skew 1-to-8, ÷1, 2, 4 Clock Generator. (P)
From old datasheet system

File Size 191.49K  /  16 Page

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    ICS853014 ICS853014BG ICS853014BGLF ICS853014BGLFT ICS853014BGT

ICST[Integrated Circuit Systems]
Part No. ICS853014 ICS853014BG ICS853014BGLF ICS853014BGLFT ICS853014BGT
OCR Text ...cts CLK0, nCLK0 inputs. LVTTL / lvcmos interface levels. Pulldown Non-inver ting differential lvpecl clock input. Inver ting differential LV...lvds C1 R3 1K R4 1K PCLK nPCLK HiPerClockS PC L K/n PCL K R1 1K R2 1K FIGURE 5C. HIPE...
Description Hex inverter buffers / drivers with high-voltage outputs 14-SOIC 0 to 70
From old datasheet system
LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-lvpecl/ECL FANOUT BUFFER
Low Skew, 1-to-5, Differential-to-lvpecl Fanout Buffer. Industrial Temperature. Improved Performance.

File Size 202.94K  /  17 Page

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    ICST[Integrated Circuit Systems]
Part No. ICS853016 ICS853016AMT ICS853016AG ICS853016AGT ICS853016AM
OCR Text ...ut. Default LOW when left open. lvcmos/LVTTL interface levels. Negative supply pin. Differential clock outputs. lvpecl interface levels. Positive supply pin. TABLE 1. PIN DESCRIPTIONS Number 1 2 3 4 5 6, 7 8 Name nQ D VBB/nD nEN VEE nQH...
Description LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V lvpecl/ECL FANOUT BUFFER
From old datasheet system
Low Skew, 1-to-2, Differential-to-lvpecl Fanout Buffer. Industrial Temperature.

File Size 215.24K  /  13 Page

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    ICS
Part No. ICS85301
OCR Text ...ut frequency: 3GHz * Translates lvcmos/LVTTL input signals to lvpecl levels by using a resistor bias network on nPCLK0, nPCLK0 * Propagation...lvds levels. The ICS85301 is packaged in a small 3mm x 3mm 16 VFQFN package, making it ideal for use...
Description 2:1 Differential-to-lvpecl Multiplexer. Industrial Temperature
From old datasheet system

File Size 289.79K  /  19 Page

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    Integrated Circuit Syst...
ICST[Integrated Circuit Systems]
Part No. ICS853031 ICS853031AYT ICS853031AY ICS853031AYLF ICS853031AYLFT
OCR Text ... any single ended input signal (lvcmos, LVTTL, GTL) to 3.3V lvpecl levels with resistor bias on nCLK or nPCLK inputs * Output skew: 20ps (ty...lvds, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulse...
Description Low Skew, 1-to-9, Differential-to-lvpecl Fanout Buffer. Industrial Temperature. Improved Performance.
From old datasheet system
Circular Connector; No. of Contacts:1; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:18; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:18-16 RoHS Compliant: No
ER 6C 6#16 PIN PLUG
Hex inverter buffers / drivers with high-voltage outputs 14-PDIP 0 to 70
   LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V lvpecl/ECL FANOUT BUFFER

File Size 226.49K  /  19 Page

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    ICS
Part No. ICS85357-01
OCR Text ...ace levels. Clock select input. lvcmos / LVTTL interface levels. Clock select input. lvcmos / LVTTL interface levels. TABLE 1. PIN DESCRI...lvds, lvpecl, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the V...
Description 4:1 or 2:1, Differential-to-3.3V lvpecl/ECL Clock Multiplexer.
From old datasheet system

File Size 157.28K  /  13 Page

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    ICS
Part No. ICS85357I-01 ICS85357-01I
OCR Text ...ace levels. Clock select input. lvcmos / LVTTL interface levels. Clock select input. lvcmos / LVTTL interface levels. TABLE 1. PIN DESCRI...lvds, lvpecl, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the V...
Description 4:1 or 2:1 Differential-to-3.3V lvpecl / ECL Clock Multiplexer. Industrial Temperature.
From old datasheet system

File Size 172.44K  /  12 Page

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    ALTERA[Altera Corporation]
Part No. EP20K200EXXXX EP20K200XXXX EP20K200EBC652 EP20K200E EP20K200 EP20K160E EP20K160EXXXX EP20K30E EP20K30EXXXX APEX20K EP20K600E EP20K1000E EP20K1500E EP20K60E EP20K100 EP20K100E EP20K300E EP20K400 EP20K400E
OCR Text ...enter tap terminated (CTT) GTL+ lvcmos LVTTL True-lvds and lvpecl data pins (in EP20K300E and larger devices) lvds and lvpecl signaling (in all BGA and FineLine BGA devices) lvds and lvpecl data pins up to 156 Mbps (in -1 speed grade device...
Description (APEP20K Series) Programmable Logic Device Family

File Size 604.10K  /  117 Page

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For lvcmos lvds lvpecl Found Datasheets File :: 1484    Search Time::3.187ms    
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