...t signal clamp condition 0V ... sync tip clamp condition 5V ... Center bias condition The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10k ). In this mode the input signal is limited to the APL 50% ...
...ation circuit v cc gnd d sync vo vs - pwm v fb ac in v str figure 1. typical application circuit internal block diagram s r q osc r sense (0.4v) olp tsd leb i fb i delay 6r r 360ns s/s 5msec uvlo v ref 7 d 8 v str gnd ...
Description
Green Mode Fairchild Power Switch (FPS) for Valley Switching Converter - Low EMI and High Efficiency
...be exact and con sistent. sync power corporation presumes no respon sibility for the penalties of use of such information or for any vio lation of patents or other rights of third parties which may result from its use. no ...