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  cmos ttl pecl lvds Datasheet PDF File

For cmos ttl pecl lvds Found Datasheets File :: 415    Search Time::1.015ms    
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    SY89538L SY89538LHGTR SY89538LHG

MICREL[Micrel Semiconductor]
Part No. SY89538L SY89538LHGTR SY89538LHG
OCR Text ...5ps output-to-output skew * ttl/cmos-compatible control logic * Five-independently programmable output frequency banks: - Four differential LVpecl output banks - One differential lvds output bank with three output pairs * Output bank synchr...
Description 3.3V Precision LVpecl and lvds Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay

File Size 625.66K  /  23 Page

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    ACS8525 ACS8525LC ACS8525P ACS8525T

Semtech Corporation
Part No. ACS8525 ACS8525LC ACS8525P ACS8525T
OCR Text ...nputs to the device support ttl/cmos and pecl/lvds. The Stand-by SEC and three Sync inputs are ttl/cmos only. The ACS8525 generates two SEC clock outputs, via one pecl/lvds and one ttl/cmos port, with spot frequencies from 2 kHz up to 311.0...
Description Line Card Protection Switch for SONET/SDH Systems

File Size 910.55K  /  112 Page

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    AZM[Arizona Microtek, Inc]
Part No. AZV99XP AZV99 AZV99LG AZV99NA AZV99NBG AZV99NDG AZV99NG AZV99T_ AZV99T
OCR Text ... Enable Polarity and Threshold (cmos/ttl or pecl) Available in a 2x2 or 3x3mm MLP Package S-Parameter (.s2p) and IBIS Model Files Available on Arizona Microtek Website PACKAGE MLP 8 (2x2x0.75) Green / RoHS Compliant / Lead (Pb) Free MLP 8 ...
Description pecl/lvds Oscillator Gain Stage & Buffer with Selectable Enable

File Size 222.80K  /  15 Page

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    TND301 MC100LVEP34 MC100EP016 MC100EP139 MC100EP16 MC100EP195 MC100EP210S MC100EP33 MC100EP90 MC100EPT20 MC100EPT21 MC10

ONSEMI[ON Semiconductor]
Part No. TND301 MC100LVEP34 MC100EP016 MC100EP139 MC100EP16 MC100EP195 MC100EP210S MC100EP33 MC100EP90 MC100EPT20 MC100EPT21 MC100EPT22 MC100EPT23 MC100EPT24 MC100EPT25 MC100EPT26 MC100LVEL91 MC100LVEL92 MC100LVEP16 MC100LVEP17
OCR Text ...ry all of which could have ECL, cmos, ttl, lvds, GTL, or HSTL inputs and outputs. Voltage Level Translation (High to Low or Low to High) Voltage Level Translation with Amplitude Change (Small/High to Large/Low or Large/Low to Small Hi...
Description Clock Management Design Using Low Skew and Low Jitter Devices

File Size 205.85K  /  8 Page

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    AZM[Arizona Microtek, Inc]
Part No. AZ12001XP AZ12000 AZ12000K AZ12000XP AZ12001 AZ12001K
OCR Text ...ode. Logic Level ECL/pecl cmos/ttl compatible INTREF INTSUM INTOUT VCOSEL cmos/ttl compatible TANK EXTVCO EXTVCO ECL/pecl DS2 DS1 cmos/ttl compatible Q Q N/C VBB VCC VCOVCC VEE ECL/pecl January 2005 * R...
Description Phase-Locked Loop Clock Generator

File Size 186.33K  /  13 Page

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