...s the background. : Frequency 2-divide function is selectable. : 3 sets (output (1) R, G, B + BLK/VC1 + VBLK1/VC2 + VBLK2 and output (2) R + RBLK/B + BBLK/G + GBLK selectable by command) When output (1) is selected, VC1 and VC2 outputs can ...
Description
ON-SCREEN CHARACTER DISPLAY CMOS IC FOR 512-CHARACTER, 12-ROW, 28-COLUMN, CAMERA-CONTAINED VCR
... 1M bytes * High-speed multiply/divide instructions: 100 ns (20 MHz, 5 V) 200 ns (10 MHz, 3 V)
0.95 to 2.8 s (20 MHz, 5 V) 1.9 to 5.6 s (...by an external device. It is not necessary to pull up or down the data bus. To invert the level of t...
... or ripple mode. APPLICATIONS * Divide-by-n counters * Programmable timers * Interrupt timers * Cycle/program counters
TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = ...
...l X = don't care APPLICATIONS * Divide-by-n counters * Programmable timers * Interrupt timers * Cycle/program counters PL H H H L X PE H H L X X TE H L X X X asynchronous synchronous inhibit counter count down preset on next LOW-to HIGH clo...
Description
8-Bit Parallel-Load Shift Registers 16-SOIC -40 to 85 HCT SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT DOWN BINARY COUNTER, PDSO16 8-bit synchronous binary down counter 8位同步二进制计数器下