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  pia Datasheet PDF File

For pia Found Datasheets File :: 103    Search Time::2.563ms    
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    Advanced Monolithic Systems, Inc.
Part No. BW1221L2CLK
OCR Text ...2nd channel clock input vref ai pia_bb reference voltage input comp ai pia_bb external capacitance connection pd di picc_bb power-down high enable iref ai pia_bb external resistor connection vdda ap vdda analog power vddd dp vddd digital po...
Description Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs BW1221L_2CLK 10位|数据资料

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    CY7C342 CY7C342-25 CY7C342-30 CY7C342-35 CY7C342B CY7C342B-15JC CY7C342B-15JI CY7C342B-20JC CY7C342B-20JI CY7C342B-25HC

Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
Part No. CY7C342 CY7C342-25 CY7C342-30 CY7C342-35 CY7C342B CY7C342B-15JC CY7C342B-15JI CY7C342B-20JC CY7C342B-20JI CY7C342B-25HC CY7C342B-25HI CY7C342B-25JC CY7C342B-25JI CY7C342B-25RC CY7C342B-25RI CY7C342B-30JC CY7C342B-30JI CY7C342B-35JC CY7C342B-35JI CY7C342B-35RI CY7C342B-35RJ 5962-8946801YA CY7C342B-30HI
OCR Text ...rogrammable Interconnect Array (pia) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the pia are the outputs of every macrocell within the device and the I/O pin feedback of every ...
Description 128-Macrocell MAX EPLDs 128宏单元最EPLDs
128-Macrocell MAX EPLDs OT PLD, 40 ns, PQCC68
128-Macrocell MAX EPLDs OT PLD, 25 ns, PQCC68
128-Macrocell MAX EPLDs UV PLD, 40 ns, CQCC68
ECONOLINE: RSZ/P - 1kVDC & 2kVDC Isolation- UL94V-0 Package Material- No Heatsink Required- No Extern. Components Required- Toroidal Magnetics- ContinuousShort Circuit Protection ( /P-Suffix)
128-Macrocell MAX® EPLD

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    CY7C343 CY7C343-20JC_JI CY7C343-35 CY7C343-30 CY7C343-20 CY7C343-35JC CY7C343-35HC_HI CY7C343-30HC_HI CY7C343-25HC_HI CY

Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
CYPRESS[Cypress Semiconductor]
Part No. CY7C343 CY7C343-20JC_JI CY7C343-35 CY7C343-30 CY7C343-20 CY7C343-35JC CY7C343-35HC_HI CY7C343-30HC_HI CY7C343-25HC_HI CY7C343-25JC_JI CY7C343-30JC_JI CY7C343-30HMB CY7C343-35HMB CY7C343-20JC/JI CY7C343-25HC/HI CY7C343-25JC CY7C343-25JC/JI CY7C343-30JC CY7C343-35HI CY7C343-35HC/HI CY7C343-30JC/JI CY7C343-30HC/HI
OCR Text ...ogrammable Inter-connect Array (pia). There are eight input pins, one that doubles as a clock pin when needed. The CY7C343 also has 28 I/O pins, each connected to a macrocell (six for LABs A and C, and eight for LABs B and D). The remaining...
Description 64-Macrocell MAX EPLD UV PLD, 35 ns, CQCC44
64-Macrocell MAX EPLD OT PLD, 35 ns, PQCC44
64-Macrocell MAX EPLD 64宏单元最大可编程逻辑器件
64-Macrocell MAX® EPLD

File Size 210.96K  /  19 Page

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    EPM7128AETC144-7 EPM7256A EPM7128A

Altera Corporation
Part No. EPM7128AETC144-7 EPM7256A EPM7128A
OCR Text ...rogrammable interconnect array (pia) continuous routing structure for fast, predictable performance PCI-compatible Bus-friendly architecture, including programmable slew-rate control Open-drain output option Programmable macrocell registers...
Description Programmable Logic Device

File Size 423.12K  /  59 Page

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    Cypress Semiconductor Corp.
Part No. CY7C344
OCR Text ...rogrammable interconnect array (pia) simplifies routing flexible macrocells increase utilization programmable clock control expander product terms implement complex logic functions ? warp2 ? low-cost vhdl compiler for cplds and plds ...
Description Universal Synchronous EPLD(通用同步EPLD) 通用同步可编程逻辑器件(通用同步可编程逻辑器件

File Size 95.64K  /  6 Page

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    Cirrus Logic, Inc.
Part No. CY7C343-25JC CY7C343-35HI CY7C343-25HC
OCR Text ...ramma- ble inter-connect array (pia). there are 8 input pins, one that doubles as a clock pin when needed. the cy7c343 also has 28 i/o pins, each connected to a macrocell (6 for labs a and c, and 8 for labs b and d). the remaining 36 macroc...
Description UV-Erasable/OTP Complex PLD UV-Erasable/OTP复杂可编程逻辑器件

File Size 214.64K  /  18 Page

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    EPM3032A

Altera Corporation
Part No. EPM3032A
OCR Text ...rogrammable interconnect array (pia) continuous routing structure for fast, predictable performance Table 1. MAX 3000A Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tCO1 (ns) ...
Description Programmable Logic Device Family

File Size 311.96K  /  41 Page

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