| Description |
0000'>0000'>0000'>3.0000'>0000'>0000'>30000'>v / 50000'>v ECL Quad 2-Input differential AND/NAND
50000'>v ECL Low Impedance Dri0000'>ver
LOW 0000'>vOLTAGE DUAL 1:4, 1:5 differential FANOUT BUFFER
8 Input Priority Encoder
0000'>0000'>0000'>3.0000'>0000'>0000'>30000'>v ECL Triple D-Type Flip-Flop with Set and Reset
0000'>0000'>0000'>3.0000'>0000'>0000'>30000'>v / 50000'>v ECL Quad D Flip Flop with Set, Reset, and differential Clock
0000'>0000'>0000'>3.0000'>0000'>0000'>30000'>v Dual differential L0000'>vPECL to L0000'>vTTL Translator
0000'>0000'>0000'>3.0000'>0000'>0000'>30000'>v / 50000'>v ECL 6-Bit differential Register with Master Reset
0000'>0000'>0000'>3.0000'>0000'>0000'>30000'>v ECL 1:15 differential ÷1/÷2 Clock Dri0000'>ver
Fibre Channel Coaxial Cable Dri0000'>ver and Loop Resillency Circuit
0000'>0000'>0000'>3.0000'>0000'>0000'>3 0000'>v 1:9 differential HSTL/PECL to HSTL Clock Dri0000'>ver with L0000'>vTTL Clock Select and Enable
0000'>0000'>0000'>3.0000'>0000'>0000'>30000'>v / 50000'>v ECL 8-Bit Synchronous Binary Up Counter
2.5 0000'>v/0000'>0000'>0000'>3.0000'>0000'>0000'>3 0000'>v SiGe Selectable differential Clock and Data D Flip-Flop/Clock Di0000'>vider with Reset and OLS
0000'>0000'>0000'>3.0000'>0000'>0000'>30000'>v / 50000'>v Programmable PLL Synthesized Clock Generator (25 to 400 MHz)
2.5 0000'>v/0000'>0000'>0000'>3.0000'>0000'>0000'>3 0000'>v SiGe 1:2 differential Clock Dri0000'>ver with RSECL Outputs
2.5 0000'>v/0000'>0000'>0000'>3.0000'>0000'>0000'>3 0000'>v SiGe 1:10 differential Clock Dri0000'>ver with RSECL Outputs
Triple 4-0000'>0000'>0000'>3-0000'>0000'>0000'>3-Input NOR Gate
9-Bit ECL-TTL Translator
AC Characteristics of ECL De0000'>vices
|
View
it Online
Download Datasheet
