...2.0V with a pulse < 3ns and - 1.5v with a pulse < 5ns 3.Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V VOUT VDD.
AC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 Param...
Description
Synchronous DRAM(512K X 16 Bit X 2 Banks) 同步DRAM(为512k × 16位2组)
... 10ns acceptable. 2.VIL(min)=-1.5v AC for pulse width 10ns acceptable. 3.Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V.
AC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter AC input hig...
... 10ns acceptable. 2.VIL(min)=-1.5v AC for pulse width 10ns acceptable. 3.Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V VOUT VDD.
AC Operating Condition
Voltage referenced to Vss = 0V, T...
... 10ns acceptable. 2.VIL(min)=-1.5v AC for pulse width 10ns acceptable. 3.Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V VOUT VDD.
AC Operating Condition
Voltage referenced to Vss = 0V, T...
... 10ns acceptable. 2.VIL(min)=-1.5v AC for pulse width 10ns acceptable. 3.Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V VOUT VDD.
AC Operating Condition
Voltage referenced to Vss = 0V, T...
Description
Synchronous DRAM(4M X 8 Bit X 4 Banks) Synchronous DRAM(4M X 8 Bit X 4 Banks) 同步DRAM4米8位4银行 Synchronous DRAM(4M X 8 Bit X 4 Banks) 同步DRAM米8位4银行 133 Mhz LVTTL synchronous DRAM, 4 M x 8 bit x 4 banks
... 10ns acceptable. 2.VIL(min)=-1.5v AC for pulse width 10ns acceptable. 3.Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V VOUT VDD.
AC Operating Condition
Voltage referenced to Vss = 0V, T...
Description
Synchronous DRAM(2M X 16 Bit X 4 Banks) Synchronous DRAM(2M X 16 Bit X 4 Banks) 同步DRAM米16位4个银行)