Description |
18-Mbit (512K x 36/1M x 18) Flow-Through sram; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V<br>36-Mbit qdr(TM)-ii sram 4-Word burst Architecture; Architecture: qdr-ii, 4 Word burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V<br>36-Mbit DDR-ii sram 2-Word burst Architecture; Architecture: DDR-ii CIO, 2 Word burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V<br>36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined sram with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V<br>72-mbit (2M x 36/4M x 18/1M x 72) Pipelined sram with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V<br>18-Mbit (512K x 36/1M x 18) Pipelined sram; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V<br>36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined sram with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V<br>72-mbit qdr(TM)-ii sram 2-Word burst Architecture; Architecture: qdr-ii, 2 Word burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V<br>18-Mbit (512K x 36/1M x 18) Flow-Through sram; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V<br>36-Mbit qdr(TM)-ii sram 2-Word burst Architecture; Architecture: qdr-ii, 2 Word burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V<br>36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through sram with NobL(TM) Architecture; Architecture: NobL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V<br>72-mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V<br>72-mbit qdr(TM)-ii sram 2-Word burst Architecture; Architecture: qdr-ii, 2 Word burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V<br>36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync sram; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V<br>36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined sram with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V<br>36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined sram with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V<br>72-mbit DDR-ii sram 2-Word burst Architecture; Architecture: DDR-ii CIO, 2 Word burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V<br>Sync sram; Architecture: qdr-ii, 2 Word burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V<br>36-Mbit DDR-ii sram 2-Word burst Architecture; Architecture: DDR-ii CIO, 2 Word burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V<br>72-mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V<br>72-mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V<br>72-mbit qdr(TM)-ii sram 4-Word burst Architecture; Architecture: qdr-ii, 4 Word burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V<br>72-mbit (2M x 36/4M x 18/1M x 72) Pipelined sram with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V<br>72-mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync sram; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V<br>72-mbit qdr(TM)-ii sram 4-Word burst Architecture (2.5 Cycle Read Latency); Architecture: qdr-ii , 4 Word burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V<br>72-mbit DDR-ii sram 2-Word burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-ii CIO, 2 Word burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V<br>36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync sram; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机<br>72-mbit DDR-ii sram 2-Word burst Architecture; Architecture: DDR-ii CIO, 2 Word burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机<br>18-Mbit (512K x 36/1M x 18) Flow-Through sram; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机<br>SINGLE-CHIP 8-bIT CMOS MICROCOMPUTER 单芯位CMOS微机<br>72-mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机<br>72-mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机<br>72-mbit qdr(TM)-ii sram 4-Word burst Architecture; Architecture: qdr-ii, 4 Word burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机<br>72-mbit qdr(TM)-ii sram 2-Word burst Architecture; Architecture: qdr-ii, 2 Word burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机<br>36-Mbit qdr(TM)-ii sram 4-Word burst Architecture; Architecture: qdr-ii, 4 Word burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机<br>SINGLE-CHIP 8-bIT CMOS MICROCOMPUTER 单芯8位CMOS微机<br>Sync sram; Architecture: qdr-ii, 2 Word burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机<br>36-Mbit DDR-ii sram 2-Word burst Architecture; Architecture: DDR-ii CIO, 2 Word burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机<br>72-mbit DDR-ii sram 2-Word burst Architecture; Architecture: DDR-ii CIO, 2 Word burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V<br>36-Mbit qdr(TM)-ii sram 2-Word burst Architecture; Architecture: qdr-ii, 2 Word burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V<br>
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