10000 system GATE 3.3 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW design 10000 system GATE LOGIC CELL ARRAY - NOT RECOMMENDED for NEW design Dual 135MHz Low-Power Op Amp
560KBITS BRAM 400000 system GATES 404 I/ - NOT RECOMMENDED for NEW design 560KBITS BRAM 400000 system GATES 404 - - NOT RECOMMENDED for NEW design 2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
300000 system GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW design 300000 system GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW design 300,000 system GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW design 2.7V to 5.5V Single Supply CMOS Op Amps 2.7V5.5V单电源CMOS运算放大 2.7V to 5.5V Single Supply CMOS Op Amps 2.7V.5V单电源CMOS运算放大