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Agilent (Hewlett-Packard)
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| Part No. |
HFBR-5984L
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| OCR Text |
...ignal detect sd: normal optical input levels tothe receiver result in a logic 1 output. low optical input levels to the receiver result in a fault condition indicated by a logic 0 output. this signal detect output can be used to drive a pec... |
| Description |
HFBR-5984L · 200 MBd SBCON Transceiver for Fibre Channel/Storage Applications
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| File Size |
358.41K /
12 Page |
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it Online |
Download Datasheet
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Freescale (Motorola)
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| Part No. |
MPC93H51
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| OCR Text |
...phase lock its outputs ont o an input reference clock. normal operation of the mpc93h51 requires a connection of one of the device outputs to the ext_fb input to close the pll feedback path. the reference clock frequency and the output d... |
| Description |
3.3V CMOS PLL Clock Generator and Driver
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| File Size |
491.73K /
12 Page |
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it Online |
Download Datasheet |
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Integrated Device Techn...
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| Part No. |
IDT8SLVP1104I
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| OCR Text |
...put pairs ? differential lvpecl input pair can accept the following differential input levels: lvds, lvpecl, cml ? differential pclkx pair...to accept single-ended levels (figures 1 and 2) ? maximum input clock frequency: 2ghz ? lvcmos inter... |
| Description |
Maximum input clock frequency
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| File Size |
367.50K /
22 Page |
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it Online |
Download Datasheet |
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Integrated Device Techn...
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| Part No. |
IDT8SLVP1102I
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| OCR Text |
...repeatability. one differential input and two low skew outputs are available. the integrated bias voltage reference enables easy interfacing of single-ended signals to the device input. the device is optimized for low power consumption and ... |
| Description |
Maximum input clock frequency
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| File Size |
657.76K /
22 Page |
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it Online |
Download Datasheet |
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Price and Availability
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