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Infineon
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| Part No. |
IHD680 IHD21
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| OCR Text |
...dieser Zeit wird der Transistor synchron mit der nachsten Einschaltflanke des Ansteuersignals wieder eingeschaltet. Mit diesem Schutzkonzept lassen sich IGBT-Halbbrucken und -Dreiphasen-Module sinnvoll und zuverlassig schutzen.
Layout de... |
| Description |
Intelligenter Halbbruken-Treiber
From old datasheet system
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| File Size |
241.48K /
24 Page |
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it Online |
Download Datasheet
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IDT
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| Part No. |
IDT29FCT520CT
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| OCR Text |
... NOUS CONTROL PRESET CLEAR ETC. synchron OUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
Octal link
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIG H PULSE
Octal link
1.5V
1.5V
tSU
tH
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| Description |
MULTILEVEL PIPELINE REGISTER
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| File Size |
55.03K /
7 Page |
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it Online |
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TRIQUINT[TriQuint Semiconductor]
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| Part No. |
GA1085
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| OCR Text |
...y maintains frequency and phase synchron-ization between the reference clock (REFCLK) and each of the outputs. TriQuint's patented output buffer design delivers a very low output-to-output skew of 150 ps (max). The GA1085's symmetrical TTL ... |
| Description |
11-Output Configurable Clock Buffer
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| File Size |
203.98K /
10 Page |
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it Online |
Download Datasheet |
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Clare.
CLARE[Clare, Inc.]
Clare Inc
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| Part No. |
MXED202
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| OCR Text |
... low, and the token output (for synchron- ization or cascading) when SHR is high. When configured as an input, this pin should always be driven. Normally low, SLIN should be driven high once per frame to enter the token into the shift regis... |
| Description |
128-Channel OLED Row Driver
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| File Size |
557.16K /
16 Page |
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it Online |
Download Datasheet |
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Price and Availability
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