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PMC[PMC-Sierra Inc]
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| Part No. |
PM4328
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| OCR Text |
...r egress per link monitoring. * unchannelized DS3 framer mode for access to the entire DS3 payload. * Supports transfer of PCM data to/from 1.544 MHz and 2.048 MHz serial interface system-side devices. Also supports a fractional T1 or E1 sy... |
| Description |
High Density T1/E1 Framer with Integrated M13 Multiplexer
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| File Size |
19.01K /
2 Page |
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M/A-COM Technology Solution...
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| Part No. |
28560-DSH-001-B 28560-DSH-001-B-15
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| OCR Text |
... data stream tsbus interfaces unchannelized data stream configurable logical channels standard ds0 (56, 64 kbps) hyperchannel (n x 64) channels? bit rate can be dynamically changed. per channel protocol mode selection per-channel... |
| Description |
HDLC Controller
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| File Size |
1,482.31K /
274 Page |
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it Online |
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pmc
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| Part No. |
2001521
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| OCR Text |
unchannelized links and up to 4 IMA groups with 1 to 8 links/group. * Link and Group State Machines implemented on-chip requiring no real time software in the data path. * Fully compliant with the ATM Forum Inverse Multiplexer for ATM (IMA)... |
| Description |
From old datasheet system
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| File Size |
25.25K /
2 Page |
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it Online |
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PMC-Serria
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| Part No. |
PM7381 1980428
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| OCR Text |
...C channels, each assigned to an unchannelized arbitrary-rate link, subject to a maximum aggregate link clock-rate of 64 MHz in each direction. * Channels assigned to links 0 to 2 support clock rates up to 52 MHz. Channels assigned to links ... |
| Description |
Frame Engine and Data Link Manager
From old datasheet system
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| File Size |
15.21K /
2 Page |
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it Online |
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pmc
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| Part No. |
2001522
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| OCR Text |
...s both independent transmit one unchannelized DS3 stream. clock (ITC) and common transmit clock * Supports up to 32 T1, E1, G.SHDSL or (CTC) modes. unchannelized links via 2-pin line * Supports all IMA Group Symmetry interfaces. modes: Symm... |
| Description |
From old datasheet system
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| File Size |
29.86K /
2 Page |
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it Online |
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PMC-Sierra Inc
PMC-Sierra, Inc.
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| Part No. |
PM7382
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| OCR Text |
... channels, each assigned to an unchannelized arbitrary-rate link, subject to a maximum aggregate link clock-rate of 64 mhz in each direction. channels assigned to links 0 to 2 support clock rates up to 52 mhz. channels assigned to l... |
| Description |
Frame Engine and Data Link Manager 32P256
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| File Size |
17.81K /
2 Page |
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it Online |
Download Datasheet |
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