...al value in the range of 27V to 40v. FIGURE 1. TYPICAL APPLICATION CIRCUIT DIAGRAM
Figure 2 illustrates some of the typical J1850 System ...3a and 3B at -50V, +100V and 200V respectively. 4. ESD Conditions - SAE J1113; Aug 1987. BUS OUT & B...
Description
FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN J1850 Bus Transceiver For Multiplex Wiring Systems
...TAGE RANGE Single supply: 5V to 40v Split supplies: 2.5V to 20V * HIGH EFFICIENCY -- |Vs-2.2V| at 2.5A typ * HIGH OUTPUT CURRENT -- 3a min (PA21A) * INTERNAL CURRENT LIMIT * LOW DISTORTION
R2 9K +28V R1 5K + 1/2 PA21 COMMAND INPUT 0/10V ...
Description
POWER DUAL OPERATIONAL AMPLIFIERS POWER DUAL OPERATIONAL AMPLIFIERS 功耗双运算放大
...urrent Peak Reverse Voltage 20V 40v Maximum RMS Voltage 14V 28V Maximum DC Blocking Voltage 20V 40v
B
3
CATHODE
2
ANODE
D G C ...3a TA = 90C 8.3ms, half sine
Suggested Solder Pad Layout
.031 .800
VF
0.45V 0.53V 100 4.0m...
Description
20 to 40 Volts 0.5 Amp Surface Mount Schottky Barrier Diode
40v * 3 Amp Continuous Current * 5 Amp Pulse Current * Low Saturation voltage * High Gain
ZTX1151A
C B
E
E-Line TO92 Compatible
...3a, IB=-250mA* IC=-3a, IB=-250mA* IC=-3a, VCE=-2V* IC=-10mA, VCE=-2V* IC=-0.5A, VCE=-2V* IC=-2A, VCE...
Description
PNP Low Sat Transistor PNP SILICON PLANAR MEDIUM POWER HIGH GAIN TRANSISTOR