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AGERE[Agere Systems]
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| Part No. |
TAAD08JU2
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| OCR Text |
...ates an ATM adaptation layer 2 (aal2) segmentation and reassembly (SAR) function for support of low-speed data or voice traffic per ITU I.363.2. Provides AAL5 SAR functionality per ITU I.363.5. Provides quality of service (QoS) connection i... |
| Description |
T1/E1/J1 ATM Processor, Versions 2.1 and 3.1
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| File Size |
1,383.51K /
174 Page |
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| Part No. |
PXB9202
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| OCR Text |
...32 hdlc hardware accelerators aal2 (cps) controller simple control of duslic, sicofi and falc ? devices via a synchronous serial interface (ssc) atm cell processing atm layer controller utopia level 1 and 2 support for up to 1... |
| Description |
?Broadband Communication Controller
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| File Size |
401.38K /
2 Page |
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FREESCALE[Freescale Semiconductor, Inc]
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| Part No. |
MSC8144
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| OCR Text |
... adaptation layer support AAL0, aal2, and AAL5. PCI designed to comply with the PCI specification revision 2.2 at 33 MHz or 66 MHz with access to all PCI address spaces. Serial RapidIO(R) 1x/4x endpoint corresponds to Specification 1.2 of t... |
| Description |
Quad Core Digital Signal Processor
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| File Size |
1,166.29K /
80 Page |
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Freescale Semiconductor, Inc
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| Part No. |
MPC82XXCVRB MPC82XXCVRE MPC82XXCVRF MPC82XXCVRI MPC82XXCVRM MPC82XXCVRP MPC82XXCVRT MPC82XXCZQB MPC82XXCZQE MPC82XXCZQF MPC82XXCZQI MPC82XXCZQM MPC82XXCZQP MPC82XXCZQT MPC82XXVRB MPC82XXVRE MPC82XXVRF MPC82XXVRI MPC82XXVRM MPC82XXVRP MPC82XXVRT MPC82XXZQB MPC82XXZQE MPC82XXZQF MPC82XXZQI MPC82XXZQM MPC82XXZQP MPC82XXZQT MPC8272EC
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| OCR Text |
...interface 31 Mphys, AAL5, AAL1, aal2, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64-K external connections -- Three serial communications controllers (SCCs) identical to those on the MPC860 supporting the digital portion... |
| Description |
PowerQUICC II⑩ Family Hardware Specifications
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| File Size |
710.38K /
60 Page |
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MOTOROLA[Motorola, Inc]
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| Part No. |
MPC859TTSD MPC859DSL MPC859P MPC859T MPC859TTS
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| OCR Text |
...peration using a "split" bus -- aal2/VBR functionality is ROM-resident Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) 32 address lines Memory controller (eight banks) -- Contains complete dynamic RAM (DRAM) controller -- ... |
| Description |
PowerQUICC⑩ Family Technical Summary
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| File Size |
272.11K /
12 Page |
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