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  cmos lvcmos Datasheet PDF File

For cmos lvcmos Found Datasheets File :: 6204    Search Time::2.047ms    
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    Xilinx, Inc.
Part No. XC2C512-10FG324I XC2C512-10FGG324I XC2C512-10FG324C XC2C512-10FGG324C XC2C512-10FT256C XC2C512-10FTG256I XC2C512-7FTG256I XC2C512-7FTG256C XC2C512-10FTG256C
OCR Text ... ? industry?s best 0.18 micron cmos cpld - optimized architecture for effective logic synthesis - multi-voltage i/o operation ? 1.5v to 3....lvcmos, lvttl, sstl, and hstl i/o implementations. see ta b le 1 for i/o standard voltages. the lvt...
Description 512 MACROCELL 1.8V ZERO POWER ISP CPLD FLASH PLD, 10 ns, PBGA324
Optimized for 1.8V systems
   XC2C512 CoolRunner-II CPLD
   Optimized for 1.8V systems

File Size 278.53K  /  24 Page

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    XAC2C128-8VQG100Q

Xilinx, Inc
Part No. XAC2C128-8VQG100Q
OCR Text ...ems Industry's best 0.18 micron cmos CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation -- 1.5V to 3....LVcmos and LVTTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard ...
Description CoolRunner-II Automotive CPLD

File Size 359.02K  /  16 Page

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    Xilinx, Inc.
XILINX INC
Part No. XC2C384-10FTG256I XC2C384-10PQG208I XC2C384-7FTG256C XC2C384-10FGG324C XC2C384-7FT256C XC2C384-10FTG256C
OCR Text ... ? industry?s best 0.18 micron cmos cpld - optimized architecture for effective logic synthesis - multi-voltage i/o operation ? 1.5v to 3....lvcmos, lvttl, sstl and hstl i/o implementations. see ta b le 1 for i/o standard voltages. the lvtt...
Description 384 MACROCELL 1.8V ZERO POWER ISP CPLD FLASH PLD, 10 ns, PBGA256
384 MACROCELL 1.8V ZERO POWER ISP CPLD FLASH PLD, 10 ns, PQFP208
384 MACROCELL 1.8V ZERO POWER ISP CPLD FLASH PLD, 7.5 ns, PBGA256
384 MACROCELL 1.8V ZERO POWER ISP CPLD FLASH PLD, 10 ns, PBGA324
   XC2C384 CoolRunner-II CPLD

File Size 304.11K  /  26 Page

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    SSTUG32866EC_G SSTUG32866EC_S SSTUG32866 SSTUG32866EC/G SSTUG32866EC/S

NXP Semiconductors
Part No. SSTUG32866EC_G SSTUG32866EC_S SSTUG32866 SSTUG32866EC/G SSTUG32866EC/S
OCR Text ...TL_18 input SSTL_18 input 1.8 V cmos outputs 1.8 V cmos output 1.8 V cmos output 1.8 V cmos output 1.8 V cmos output open-drain output - ...LVcmos. All data outputs are 1.8 V cmos drivers that have been optimized to drive the DDR2 DIMM load...
Description 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer

File Size 142.48K  /  28 Page

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    XC2C256-7TQG144C XC2C256-7TQG144I XC2C256-7FTG256C XC2C256-7FTG256I XC2C256-7VQG100C XC2C256-7VQG100I XC2C256-6VQG100C X

Xilinx, Inc
Part No. XC2C256-7TQG144C XC2C256-7TQG144I XC2C256-7FTG256C XC2C256-7FTG256I XC2C256-7VQG100C XC2C256-7VQG100I XC2C256-6VQG100C XC2C256-6FT256C XC2C256-7FT256C XC2C256-6CPG132C XC2C256-7CPG132C XC2C256-6TQ144C XC2C256-7PQ208C XC2C256-7PQ208I XC2C256-6PQ208C XC2C256-7CP132C XC2C256-7CP132I XC2C256-7FT256I XC2C256-6FTG256C
OCR Text ...ent Industry's best 0.18 micron cmos CPLD - Optimized architecture for effective logic synthesis. Refer to the CoolRunnerTM-II family data s...LVcmos standard is used in 3.3V, 2.5V, 1.8V applications. Both HSTL and SSTL I/O standards make use ...
Description CoolRunner-II CPLD

File Size 404.16K  /  24 Page

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