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TI store
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| Part No. |
TMS77C82
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| OCR Text |
...rature ranges clock options divide-by-1 (2 mhz 5 mhz sysclk) phase-locked loop (pll) divide-by-4 (0.5 mhz 5 mhz sysclk) supply voltage (v cc ) 5 v 10% 16-bit general purpose timer software configurable as a 16-bit event cou... |
| Description |
<font color=red>[Old version datasheet]</font> 8-BIT MICROCONTROLLER
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| File Size |
739.18K /
50 Page |
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it Online |
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ONSEMI[ON Semiconductor]
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| Part No. |
CS8441YN8 CS8441 CS8441-D
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| OCR Text |
Divide by Select
The CS8441 is a Stepper Motor Driver that implements an H-Bridge design in order to drive two coils in an eight step sequence per revolution in the divide by 1 mode; 16 step sequence in the divide by 2 mode. The H-Bridge i... |
| Description |
Stepper Motor Controller/Driver
Stepper Motor Driver with Divide by Select
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| File Size |
54.79K /
8 Page |
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it Online |
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ICST[Integrated Circuit Systems]
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| Part No. |
ICS252MPLF ICS252 ICS252MIP ICS252MIPLF ICS252MP
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| OCR Text |
...OTP ROM with PLL Values
PLL1 Divide Logic and Output Enable Control CLK1 CLK2
PLL2
X1 Crystal X2 External capacitors are required. ...by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be... |
| Description |
From old datasheet system
Field Programmable Dual Output SS VersaClock Synthesizer
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| File Size |
88.42K /
9 Page |
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it Online |
Download Datasheet |
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ZF Electronics, Corp.
ONSEMI[ON Semiconductor]
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| Part No. |
CS4161YN8 CS4161 CS4161-D CS4161/D
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| OCR Text |
Divide by Select and UVLO
The CS4161 is a Stepper Motor Driver that implements an H-Bridge design in order to drive two coils in an eight step sequence per revolution in the divide by 1 mode; 16 step sequence in the divide by 2 mode. The H... |
| Description |
85 mA Dual H-Bridge Odometer Driver with Divide by Select and UVLO 八十五毫安双H桥驱动器，里程表除以选择和UVLO
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| File Size |
55.96K /
8 Page |
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it Online |
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Integrated Device Techn...
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| Part No. |
309RILF 309RILFT
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| OCR Text |
...trum gnd 2 3 vdd pdts pll2 pll3 divide logic and output enable control clk1 clk9 clk8 clk7 clk6 clk5 clk4 clk3 clk2 x2 crystal or clock inpu...by bringing the pdts pin to ground. when pdts is brought high, after the st robe pin in brought h... |
| Description |
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH
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| File Size |
108.20K /
10 Page |
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it Online |
Download Datasheet |
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TI store
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| Part No. |
TMS370
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| OCR Text |
...rature ranges clock options divide-by-1 (2 mhz 5 mhz sysclk) phase-locked loop (pll) divide-by-4 (0.5 mhz 5 mhz sysclk) supply voltage (v cc ) 5 v 10% programmable acquisition and control timer (pact) module input capture on... |
| Description |
<font color=red>[Old version datasheet]</font> 8-BIT MICROCONTROLLER
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| File Size |
643.76K /
43 Page |
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it Online |
Download Datasheet |
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IRC Advanced Film
ICST[Integrated Circuit Systems]
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| Part No. |
ICS270PGLF ICS270 ICS270PG ICS270PGI ICS270PGILF
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| OCR Text |
...th PLL Values
CLK1 PLL1 CLK2 Divide Logic and Output Enable Control CLK3 CLK4 CLK5 CLK6 CLK7 CLK8
PLL2
VIN PLL3 X1 Crystal X2 Exter...by the particular crystal used (manufacture and frequency) and by PCB layout. The typical required c... |
| Description |
CAP 10UF 16V 10% TANT SMD-3216-18 TR-7 三锁相环现场可编程VCXO的时钟合成器
Triple PLL Field Programmable VCXO Clock Synthesizer
From old datasheet system
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| File Size |
99.73K /
8 Page |
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it Online |
Download Datasheet |
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Price and Availability
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