...
PA1/PPO1
PA1 PA1 direction IP Data bus
Hi-Z
1 pin
RD (Port A)
Port A
PPO data
PA2/PPO2 to PA4/PPO4
Port A data
Hi-Z...65 0.12 M
+ 0.35 2.75 - 0.15
0.15
0 to 15 DETAIL A
0.8 0.2
(16.3)
PACKAGE STRUCTU...
...
PA1/PPO1
PA1 PA1 direction IP Data bus
Hi-Z
1 pin
RD (Port A)
Port A
PPO data
PA2/PPO2 to PA4/PPO4
Port A data
Hi-Z...65
+ 0.15 0.3 - 0.1
30 0.13 M + 0.35 2.75 - 0.15
+ 0.2 0.1 - 0.05
0.15
DETAIL A
0....
...REFERENCE DATA SYMBOL VDDD VDDA IP(tot) VI Vo RL ILE DLE Tamb PARAMETER digital supply voltage (pins 2, 21 and 41) analog supply voltage (pi...65 C CLUTS 3 256 8 MATRIX ENCODER RTCI 69 67 Y outputs to monitor/TV CVBS TRIPLE DACs OUTPUT BUFFER...
...S00 (1st edition) (Previous No. IP-3680) Date Published June 1996 P Printed in Japan
The mark H shows major revised points.
(c)
199...65 VSS P00/RTP0 P01/RTP1 P02/RTP2 P03/RTP3 P04/PWM0 P05/ TCUD/PWM1 P06/ TIUD/TO40 P07/ TCLRUD
WDTO ...
...S00 (1st edition) (Previous No. IP-3538) Date Published August 1996 P Printed in Japan
The mark
* shows major revised points.
(c)
19...65.5 kHz (main system clock: at 4.19 MHz operation) * F, 750, 375, 93.8 kHz (main system clock: at 6...
...S00 (1st edition) (Previous No. IP-3657) Date Published November 1996 P Printed in Japan
The mark
* shows major revised points.
(c)
...65.5 kHz (main system clock: during 4.19-MHz operation) * , 750, 375, 93.8 kHz (main system clock: d...
...t A direction "0" when reset
IP
Input protection circuit
Hi-Z
RD (Port A) Port A input selection "0" when reset A/D converter
...65
40
+ 0.4 14.0 - 0.1
17.9 0.4
A 80 25 + 0.2 0.1 - 0.05
0.8 0.2 M
+ 0.15 0.35 - ...