LvDS is a low noise, low-voltage signal scheme that uses a small current (typically 3.5mA) to generate a voltage drop across a 100Ω resistor to convey information or data
5.1 v AND 8 v DUAL-vOLTAGE regulATOR WITH DISABLE AND RESET FUNCTIONS very low drop voltage regulators with inhibit Ultra fast low-loss controlled avalanche rectifiers From old datasheet system
A dual mode Low Drop Out (LDO) voltage regulator macrocell with a fixed 1.8v output voltage, rated for loads of up to 80 mA and as low as 5 mA. A typical application is baseband memory in mobile terminals.
CAP CER DISC 1500PF 2Kv 10% RAD 5-v low-drop Fixed voltage regulator 5 v FIXED POSITIvE LDO regulATOR, 0.7 v DROPOUT, PSFM5 5-v low-drop Fixed voltage regulator 5 v FIXED POSITIvE LDO regulATOR, 0.7 v DROPOUT, PSSO5 CAP CER DISC 180PF 2Kv 10% RAD 5 - v低拖放固定稳压器 5-v low-drop Fixed voltage regulator 5 - v低拖放固定稳压器
DUAL ULTRA LOW DROP-LOW NOISE BICMOS vOLTAGE REG. FOR USE WITH vERY LOW ESR OUT. CAPACITORS DUAL ULTRA LOW DROP-LOW NOISE BICMOS vOLTAGE REG. FOR USE WITH vERY LOW ESR OUT. CAPACITORS 双超低压降低噪声BICMOS工艺电压退订。至于一些使用低ESR输出。电容器