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divide-by-16 17 Datasheet PDF File

For divide-by-16 17 Found Datasheets File :: 4584 Search Time::1.187ms
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				List of Unclassifed Man... PHILIPS[Philips Semiconductors] NXP Semiconductors
Part No.	HEF4059B HEF4059BD HEF4059BF HEF4059BN HEF4059BP HEF4059BT
OCR Text	...EC HEF4059B LSI Programmable divide-by-n counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Programmable divide-by-n counter DESCRIPTION The HEF4059B is...
Description	Programmable divide-by-n counter
File Size	58.40K / 6 Page	View it Online	Download Datasheet

				ZILOG[Zilog, Inc.]
Part No.	Z86E73 Z86L74 Z86E72 Z86E74 Z86L73
OCR Text	...e VIN = OV, VCC @ 8.0 MHz Clock divide-by-16 @ 8.0 MHz Clock divide-by-16 @ 8.0 MHz STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is Running STOP Mode VIN = OV, VCC WDT is ...
Description	OTP IR Microcontrollers INFRARED REMOTE CONTROLLERS
File Size	121.05K / 19 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9176-01 ICS9176M-01 AV9176M-01 ICS9176Q-01
OCR Text	...e input frequency in the normal divide-by-1 mode. In this case, the output can go to 120 MHz with a 60 MHz input clock. The maximum rise and fall time of an output is 1ns and each is TTL-compatible with a 40mA symmetric drive. The ICS9176-0...
Description	Low Skew Output Buffer
File Size	377.43K / 8 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9178-03 ICS9178Y-03
OCR Text	...5% and 60 - 170 MHz at 3.3V 5%. Divide ratios assume BCLK is externally fed back to FBCLK. The 2XPCLK series or Thevinen trace terminations ...by the device. 3 ICS9178-03 Absolute Maximum Ratings VDD referenced to GND . . . . . . . . . . ...
Description	245 MHz Clock Generator and Integrated Buffer for PowerPC™
File Size	490.53K / 8 Page	View it Online	Download Datasheet

				CYPRESS[Cypress Semiconductor] CYPRESS SEMICONDUCTOR CORP
Part No.	IMIZ9972BA IMIZ9972BAT IMIZ9972 Z9972
OCR Text	...Inputs. These inputs select the divide ratio at FB_OUT output. See Table 2. VCO Divider Select Input. When set LOW, the VCO output is divided by 2. When set HIGH, the divider is bypassed. See Table 1. Feedback Clock Input. Connect to FB_OUT...
Description	Output frequency up to 125 MHz 3.3V, 125-MHz, Multi-Output Zero Delay Buffer 3.3V/ 125-MHz/ Multi-Output Zero Delay Buffer
File Size	86.56K / 9 Page	View it Online	Download Datasheet

				SANYO[Sanyo Semicon Device]
Part No.	LC72130 LC72130M
OCR Text	.........pulse swallower (built-in divide-by-two prescaler) -- AMIN: 2 to 40 MHz ..............pulse swallower 0.5 to 10 MHz ...........direct division * IF counter -- IFIN: 0.4 to 12 MHz ...........AM/FM IF counter * Reference frequencies -- ...
Description	AM/FM PLL Frequency Synthesizer CMOS LSI From old datasheet system
File Size	303.37K / 22 Page	View it Online	Download Datasheet

				SANYO[Sanyo Semicon Device]
Part No.	LC72131M LC72131
OCR Text	.........pulse swallower (built-in divide-by-two prescaler) -- AMIN: 2 to 40 MHz ..............pulse swallower 0.5 to 10 MHz ...........direct division * IF counter -- IFIN: 0.4 to 12 MHz ...........AM/FM IF counter * Reference frequencies -- ...
Description	From old datasheet system CMOS LSI AM/FM PLL Frequency Synthesizer
File Size	402.78K / 23 Page	View it Online	Download Datasheet

				SANYO[Sanyo Semicon Device]
Part No.	LC72133M LC72133V
OCR Text	.........pulse swallower (built-in divide-by-two prescaler), VDD 2.7 V 10 to 130 MHz ..........pulse swallower (built-in divide-by-two prescaler), VDD 3.0 V -- AMIN: 2 to 40 MHz ..............pulse swallower 0.5 to 10 MHz ...........direct d...
Description	PLL Frequency Synthesizer for Electronic Tuning
File Size	299.12K / 22 Page	View it Online	Download Datasheet

				SANYO[Sanyo Semicon Device]
Part No.	LC72134M
OCR Text	...llower technique (With built-in divide-by-2 prescaler) -- FMINb (sub): 10 to 160 MHz ... Pulse swallower technique (With built-in divide-by-2 prescaler) -- AMIN (main): 0.5 to 40 MHz ... Pulse swallower and direct division techniques * IF c...
Description	Dual PLL Frequency Synthesizer for FM Tuner Systems CMOS IC
File Size	459.96K / 27 Page	View it Online	Download Datasheet

For divide-by-16 17 Found Datasheets File :: 4584 Search Time::1.187ms
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