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Fairchild Semiconductor Corporation
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| Part No. |
lvds
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| OCR Text |
...ce technologies such as RS-422, pecl, and LVpecl. This compatibility makes upgrades to higher performance possible with minimum redesign.
...lvds Description and Family Characteristics
Fairchild does not assume any responsibility for use of... |
| Description |
lvds Description and Family Characteristics
lvds Description and Family Characteristics
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| File Size |
211.61K /
2 Page |
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Agere Systems
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| Part No. |
OR4E2 OR4E4 OR4E6 OR4E10
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| OCR Text |
.../O. -- Single-ended: GTL, GTL+, pecl, SSTL3/2 (class I & II), HSTL (Class I, III, IV), zero-bus turn-around (ZBT*), and double data rate (DDR). -- Double-ended: LDVS, bused-lvds, LVpecl. -- Customer defined: Ability to substitute arbitrary ... |
| Description |
Field-Programmable Gate Arrays
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| File Size |
1,412.01K /
124 Page |
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it Online |
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ICS
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| Part No. |
M2026
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| OCR Text |
...(1, 4, 8, 32, TriState)
CML or pecl Options
FOUT nFOUT
Figure 3: Detailed Block Diagram
DIVIDER SELECTION TABLES
Mfin Divider Loo...lvds) or a single-ended clock input (LVCMOS or LVTTL on the non-inverting input).
A single-ended re... |
| Description |
SAW PLL for Frequency Translation with automatic reference clock reselection, Loss of Lock indicator, and Hitless Switching options
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| File Size |
333.73K /
12 Page |
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FREESCALE[Freescale Semiconductor, Inc]
Freescale Semiconductors
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| Part No. |
MC100ES6014 MC100ES6014EJR2 MC100ES6014DT MC100ES6014DTR2 MC100ES6014EJ
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| OCR Text |
pecl/HSTL/lvds Clock Driver
The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/pecl input signals can be either differential or... |
| Description |
2.5 V/3.3 V 1:5 Differential ECL/pecl/HSTL/lvds Clock Driver
2.5V / 3.3V 1:5 Differential ECL/pecl/HSTL/lvds Clock Driver
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| File Size |
247.27K /
8 Page |
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Price and Availability
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