| |
|
 |
INTEGRATED SILICON SOLUTION INC
|
| Part No. |
IS64LF6432-8.5TQA2
|
| OCR Text |
...individual bytes to be written. bw1 controls dq1-dq8, bw2 controls dq9-dq16, bw3 controls dq17-dq24, bw4 controls dq25-dq32, condi- ti...7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 7... |
| Description |
64K X 32 CACHE SRAM, 8.5 ns, PQFP100
|
| File Size |
108.35K /
17 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Integrated Silicon Solution, Inc.
|
| Part No. |
IS61SP12836
|
| OCR Text |
...individual bytes to be written. bw1 controls dqa, bw2 controls dqb, bw3 controls dqc, bw4 controls dqd, conditioned by bwe being lo...7 7.5 10 ns frequency 200 166 150 133 100 mhz 128k x 32, 128k x 36 synchronous pipelined static ram
... |
| Description |
128K x 36 Synchronous Pipelined SRAM(128K x 36 同步流水线静态RAM) 128K的同步流水线× 36的SRAM28K的36同步流水线静态内存）
|
| File Size |
127.18K /
15 Page |
View
it Online |
Download Datasheet |
| |
|
|
GSI Technology, Inc.
|
| Part No. |
GS84118B-150I
|
| OCR Text |
...v ), and write control inputs ( bw1 , bw2 , bwe , gw, de ) are synchronous and are controlled by a positive-edge-triggered clock (clk)....7.5 ns 4.0 ns 250 ma 10 ns 4.5 ns 190 ma flow through 2-1-1-1 t kq t cycle i dd 8.5 ns 10 ns 190 ma... |
| Description |
256K x 18 Sync Cache Tag 256K X 18 CACHE TAG SRAM, 10 ns, PBGA119
|
| File Size |
723.81K /
30 Page |
View
it Online |
Download Datasheet |
| |
|
|
IDT
|
| Part No. |
IDT71V2558SA IDT71V2558S IDT71V2556SA IDT71V2556S
|
| OCR Text |
... linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expansion 3.3V power supply (5%), 2....7 1.7 -0.3
(1)
Typ. 3.3 2.5 0
____ ____ ____
Max. 3.465 2.625 0 VDD +0.3 VDDQ +0.3 0.7
(2)
... |
| Description |
128K x 36, 256K x 18 3.3V Synchronous ZBT? SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
|
| File Size |
513.18K /
28 Page |
View
it Online |
Download Datasheet |
| |
|
|
AMIC Technology, Corp.
|
| Part No. |
A67L7332SERIES A67L7336SERIES A67L8316SERIES A67L8318SERIES A67L7332E-4 A67L7332E-4.2 A67L7332E-4.5 A67L8318E-4.2 A67L8316E-4.2 A67L7336E-4.2 A67L7336E-4 A67L7336E-4.5 A67L8316E-4 A67L8318E-4 A67L8318E-4.5
|
| OCR Text |
...e ( cen ), byte write enables ( bw1 , bw2 , bw3 , bw4 ) and read/write (r/ w ). asynchronous inputs include the output enable ( oe ), clock ...7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 30 27 29 80 79 78 77 76 75 74 72 73 71 7... |
| Description |
Cycle time:7ns; access time:4.5ns; 256K x 16 LVTTL, pipelined DBA SRAM
Cycle time:7ns; access time:4ns; 256K x 16 LVTTL, pipelined DBA SRAM
Cycle time:7ns; access time:4.2ns; 256K x 16 LVTTL, pipelined DBA SRAM
Cycle time:7ns; access time:4.2ns; 128K x 32 LVTTL, pipelined DBA SRAM
Cycle time:7ns; access time:4ns; 128K x 32 LVTTL, pipelined DBA SRAM
256K X 16/18. 128K X 32/36 LVTTL. Pipelined DBA SRAM 256 × 16/18128K的X 32/36 LVTTL等级。流水线数据库管理员的SRAM
256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM
Cycle time:7ns; access time:4.5ns; 128K x 32 LVTTL, pipelined DBA SRAM
Cycle time:7.5ns; access time:4.2ns; 128K x 32 LVTTL, pipelined DBA SRAM
Cycle time:8.5ns; access time:4.5ns; 128K x 32 LVTTL, pipelined DBA SRAM
|
| File Size |
384.78K /
19 Page |
View
it Online |
Download Datasheet |
| |
|
|
GSI Technology, Inc.
|
| Part No. |
GS84118AGT-150 GS84118AT-100I
|
| OCR Text |
...v ), and write control inputs (bw1 , bw2 , bwe , gw, de ) are synchronous and are controlled by a positive-edge-triggered clock (clk). ou...7.5 ns 4.0 ns 250 ma 10 ns 4.5 ns 190 ma flow through 2-1-1-1 t kq t cycle i dd 8.5 ns 10 ns 190 ma... |
| Description |
256K x 18 Sync Cache Tag 256K X 18 CACHE TAG SRAM, 10 ns, PQFP100
256K x 18 Sync Cache Tag 256K X 18 CACHE TAG SRAM, 12 ns, PQFP100
|
| File Size |
404.94K /
20 Page |
View
it Online |
Download Datasheet |
| |
|
|
Winbond
|
| Part No. |
W25P010A W25P010AS
|
| OCR Text |
... clk, ce_1, ce2, ce_3, gw, bwe, bw1, bw2, bw3, bw4, oe, adv, adsc, adsp, zz, ft, lbo); parameter maxDepth = 32768; //32k parameter maxAddr =...7:0]; if (~bw_en2) array_quad2[addr] <= din[15:8]; if (~bw_en3) array_quad3[addr] <= din[23:16]; if ... |
| Description |
From old datasheet system
32k x 32 burst pipelined SRAM
|
| File Size |
46.51K /
8 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
