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  clock data multiplexer 2 5 v 3 Datasheet PDF File

For clock data multiplexer 2 5 v 3 Found Datasheets File :: 150+       Page :: | 1 | 2 | 3 | 4 | 5 | <6> | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |   

    Elite Semiconductor Mem...
Part No. M13S2561616A-2A
Description Double-data-rate architecture, two data transfers per clock cycle

File Size 1,237.68K  /  49 Page

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    W9751G6KB-18 W9751G6KB-25 W9751G6KB-3 W9751G6KB25A W9751G6KB25I W9751G6KB25K

Winbond
Part No. W9751G6KB-18 W9751G6KB-25 W9751G6KB-3 W9751G6KB25A W9751G6KB25I W9751G6KB25K
Description Double data Rate architecture: two data transfers per clock cycle

File Size 1,138.04K  /  87 Page

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    W631GG6KB-15 W631GG6KB12A W631GG6KB12I W631GG6KB12K W631GG6KB15I W631GG6KB-11 W631GG6KB-12 W631GG6KB15A W631GG6KB15K

Winbond
Part No. W631GG6KB-15 W631GG6KB12A W631GG6KB12I W631GG6KB12K W631GG6KB15I W631GG6KB-11 W631GG6KB-12 W631GG6KB15A W631GG6KB15K
Description Double data Rate architecture: two data transfers per clock cycle

File Size 1,961.75K  /  158 Page

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    Elite Semiconductor Mem...
Part No. M14D2561616A-2E
Description Internal pipelined double-data-rate architecture; two data access per clock cycle

File Size 1,072.53K  /  61 Page

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    Elite Semiconductor Mem...
Part No. M14D5121632A-2K
Description Internal pipelined double-data-rate architecture; two data access per clock cycle

File Size 769.45K  /  64 Page

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    SH713609 SH7137

Renesas Electronics Corporation
Part No. SH713609 SH7137
Description SCI clock Synchronous Simultaneous Transmit and Receive of Serial data and DTC data Transfer

File Size 808.57K  /  22 Page

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    NB6L572M NB6L572MMNG NB6L572MMNR4G

ON Semiconductor
Part No. NB6L572M NB6L572MMNG NB6L572MMNR4G
Description 6L SERIES, LOW SKEW clock DRIvER, 2 TRUE OUTPUT(S), 0 INvERTED OUTPUT(S), QCC32
2.5v / 3.3v Differential 4:1 Mux to 1:2 CML clock/data Fanout / Translator
2.5v / 3.3v Differential 4:1 Mux to 1:2 CML clock/data Fanout / Translator

File Size 148.82K  /  9 Page

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    W9412G6JH W9412G6JH-5

Winbond
Part No. W9412G6JH W9412G6JH-5
Description 2M ?4 BANKS ?16 BITS DDR SDRAM
Double data Rate architecture; two data transfers per clock cycle

File Size 856.09K  /  53 Page

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    MC100EP01 MC10EP445 MC10H172FNR2 MC100EL29 MC100H600FN MC100H600FNR2 MC10H424 MC10H117FNR2 MC100EP016AFA MC10E016 MC100E

ON Semiconductor
Part No. MC100EP01 MC10EP445 MC10H172FNR2 MC100EL29 MC100H600FN MC100H600FNR2 MC10H424 MC10H117FNR2 MC100EP016AFA MC10E016 MC100EP809 MC100EPT622FAR2 MC10EP131 MC100EL1648MEL MC100LvEL31 MC10H161FNR2 MC100ELT25DR2 MC100EL90DWR2 MC100EL56DWR2 MC10H330 MC100E101 MC100LvEL29DWR2 MC10H209MEL
Description 3.3v / 5v ECL 4-Input OR/NOR
3.3v / 5vECL 8-Bit Serial/Parallel Converter
Dual Binary 1-4-Decoder (High)
5v ECL Dual Differential data and clock D Flip-Flop With Set and Reset
9-Bit TTL-ECL Translator
Quad TTL-ECL Translator
Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
3.3v / 5v ECL 8-Bit Synchronous Binary Up Counter
3.3 v 1:9 Differential HSTL/PECL to HSTL clock Driver with LvTTL clock Select and Enable
3.3v 10-bit LvTTL/LvCMOS to LvPECL Translator
3.3v / 5v ECL Quad D Flip Flop with Set, Reset, and Differential clock
5v ECL voltage Controlled Oscillator
3.3v ECL D-Type Flip-Flop with Set and Reset
Binary to 1-8 Decoder (Low)
Differential -5v ECL To TTL Translator
-3.3v / -5v Triple ECL Input to PECL Output Translator
5v ECL Dual Differential 2:1 multiplexer
Quad MSTR
5v ECL Quad 4-Input OR/NOR Gate
3.3v ECL Dual Differential data and clock D-Type Flip-Flop with Set and Reset
Dual 4-5-Input OR/NOR

File Size 52.36K  /  10 Page

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    W972GG6JB W972GG6JB-25

Winbond
Part No. W972GG6JB W972GG6JB-25
Description 16M ?8 BANKS ?16 BIT DDR2 SDRAM
Double data Rate architecture: two data transfers per clock cycle

File Size 1,125.88K  /  87 Page

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For clock data multiplexer 2 5 v 3 Found Datasheets File :: 150+       Page :: | 1 | 2 | 3 | 4 | 5 | <6> | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |   

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