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  ddr-4 Datasheet PDF File

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    ICS950202

Integrated Circuit Syst...
ICS
Integrated Circuit Systems
Part No. ICS950202
OCR Text ...Intel 845 chipset with PC133 or DDR memory. It provides all necessary clock signals for such a system. The ICS950202 is part of a whole new ...4, 8, 14, 19, 25, 29, 32, 36, 42 22, 21, 20 5 VDD X1 X2 GND 3V 66 (3:1) P C IC LK 7 FS 0 PCICLK8 6 F...
Description CK408 Clock Supporting Brookdale Platforms with Indexed Write, 48-Pin
Programmable Timing Control HubTM for P4TM 可编程定时控制HubTMP4TM

File Size 159.72K  /  19 Page

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    ICS950902 ICS950902YFLF-T ICS950902YGLF-T

ICST[Integrated Circuit Systems]
Part No. ICS950902 ICS950902YFLF-T ICS950902YGLF-T
OCR Text ...4.318MHz * 12 - SDRAM (6 pair - DDR) selectable Key Specifications: * CPU_CS - CPUT/C: <250ps * CPU_CS - AGP: <250ps * CPU - DDR/SD: <250ps ...4.0ns Features/Benefits: * Programmable output frequency. * Programmable output divider ratios. * Pr...
Description Programmable Timing Control Hub⑩ for P4⑩
Programmable Timing Control Hub for P4

File Size 181.59K  /  20 Page

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    ICS950905

ICS
Integrated Circuit Systems
Part No. ICS950905
OCR Text ...IA P4X266 chipset with PC133 or DDR memory. Output Features: * 2 - Pair of differential CPU clocks @ 3.3V * 1 - Pair of differential push pu...4.0ns Pin Configuration **SEL24_48/REF0 VDDREF GND X1 X2 VDD48 *FS3/48MHz *FS2/24_48MHz GND *FS0...
Description Programmable Timing Control Hub⑩ for P4⑩
Programmable Timing Control Hub for P4 (A)

File Size 203.32K  /  18 Page

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    ICS950908

ICST[Integrated Circuit Systems]
Part No. ICS950908
OCR Text ... * CPU_CS - AGP: <250ps * CPU - DDR/SD: <250ps * PCI - PCI: <500ps Frequency Table FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1...4 VDDAGP 5 *MODE/AGPCLK0 6 *SEL_408/K7/AGPCLK1 7 *(PCI_STOP#)AGPCLK2 8 GNDAGP 9 **FS1/PCICLK_F 10 **...
Description Programmable Timing Control Hub⑩ for P4⑩
Programmable Timing Control Hub for P4

File Size 276.17K  /  22 Page

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    ICS950910 ICS950910YFLF-T

ICST[Integrated Circuit Systems]
Part No. ICS950910 ICS950910YFLF-T
OCR Text ... * CPU_CS - AGP: <250ps * CPU - DDR: <250ps * PCI - PCI: <500ps * CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns Features/Benefits: * Programmable output frequency. * Programmable output divider ratios. * Programmable output rise/fall tim...
Description Clock Synthesizer
Programmable Timing Control Hub for P4

File Size 180.35K  /  20 Page

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    IDT79RC32438 79RC32K438266BB 79RC32K438233BB 79RC32438 79RC32K438200BB 79RC32K438-200BB 79RC32K438200BBI 79RC32K438-200B

IDT[Integrated Device Technology]
Part No. IDT79RC32438 79RC32K438266BB 79RC32K438233BB 79RC32438 79RC32K438200BB 79RC32K438-200BB 79RC32K438200BBI 79RC32K438-200BBI 79RC32K438-233BB 79RC32K438233BBI 79RC32K438-233BBI 79RC32K438-266BB 79RC32K438266BBI 79RC32K438300BB 79RC32K438-300BB 79RC32K438300BBI
OCR Text ...2.5 of the EJTAG Specification DDR Memory Controller - Supports up to 2GB of DDR SDRAM - 2 chip selects (each chip select supports 4 internal DDR banks) - Supports 16-bit or 32-bit data bus width using 8, 16, or 32-bit devices - Supports 6...
Description IDTTM InterpriseTM Integrated Communications Processor

File Size 615.40K  /  59 Page

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    IRU3037 IRU3037A IRU3037ACF IRU3037ACS IRU3037CF IRU3037CS IRF7457

IRF[International Rectifier]
Part No. IRU3037 IRU3037A IRU3037ACF IRU3037ACS IRU3037CF IRU3037CS IRF7457
OCR Text ...t is detected. APPLICATIONS DDR memory source sink Vtt application Low cost on-board DC to DC such as 5V to 3.3V, 2.5V or 1.8V Graphic C...4 8 SS/SD 7 Comp 6 Vc 5 HDrv Fb 1 Vcc 2 LDrv 3 Gnd 4 8 SS/SD 7 Comp 6 Vc 5 HDrv JA=124C/...
Description 8-PIN SYNCHRONOUS PWM CONTROLLER

File Size 219.64K  /  21 Page

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    STI5100 STI5100-MBOARD STI5100-REF STI5100-STDVB STI5100ZUA -STI5100-STDVB

STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
意法半导
Part No. STI5100 STI5100-MBOARD STI5100-REF STI5100-STDVB STI5100ZUA -STI5100-STDVB
OCR Text ...z which, when combined with the DDR memory interface, gives the new device exceptional levels of performance. The new chip also includes a u...4 display planes 2, 4 and 8 bpp CLUT graphics, 256 x 30 bits (AYCBCr) CLUT entries 16 bpp true col...
Description STB5100 data briefing
Low-cost interactive set-top box decoder

File Size 75.71K  /  2 Page

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