...to 160 MHz.....Pulse swallower (divide-by-two prescaler built in) -- AMIN: 2 to 40 MHz.........Pulse swallower 0.5 to 10 MHz......Direct division * IF counter IFIN: 0.4 to 12 MHz................For use as an AM/FM IF counter * Reference fre...
Description
CMOS LSI PLL Frequency Synthesizer for Electronic Tuning
...to 160 MHz.....Pulse swallower (divide-by-two prescaler built in) -- AMIN: 2 to 40 MHz.........Pulse swallower 0.5 to 10 MHz......Direct division * IF counter IFIN: 0.4 to 12 MHz................For use as an AM/FM IF counter * Reference fre...
...to 160 MHz.....Pulse swallower (divide-by-two prescaler built in) -- AMIN: 2 to 40 MHz.........Pulse swallower 0.5 to 10 MHz......Direct division * IF counter IFIN: 0.4 to 12 MHz................For use as an AM/FM IF counter * Reference fre...
...ting IN or CLK IN, setting the divide ratio when IN is selected, and specifying the use of expansion/normal, data store by DMA cycle or MPU cycle, presence of fixed beginning data of specified length added at the beginning of data output,...
Description
From old datasheet system LINE SCAN BUFFER with 16BIT MPU BUS COMPATIBLE LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
...lock: 2 clock cycle resolution, divide by 2/8/32 selective Other interval timers * 16-bit timer: 3 channels (U-TIMER) * PWM timer: 4 channels * Watchdog timer: 1 channel Bit search module First bit transition "1" or "0" from MSB can be dete...
...lock: 2 clock cycle resolution, divide by 2/8/32 selective Other interval timers * 16-bit timer: 3 channels (U-TIMER) * PWM timer: 4 channels * Watchdog timer: 1 channel Bit search module First bit transition "1" or "0" from MSB can be dete...
...lock: 2 clock cycle resolution, divide by 2/8/32 selective Other interval timers * 16-bit timer: 3 channels (U-TIMER) * PWM timer: 4 channels * Watchdog timer: 1 channel Bit search module First bit transition "1" or "0" from MSB can be dete...
...o 2.0Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both 4-bit conversion and a two chip 8-bit conversion function. The conversion sequence was chosen to convert the first serial bit to Q0, the second to Q1 etc.
MC10E...
Description
From old datasheet system 4-BIT SERIAL/ PARALLEL CONVERTER
...o 1.3Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both 4-bit conversion and a two chip 8-bit conversion function. The conversion sequence was chosen to convert the parallel data into a serial stream from bit D0 to D3. ...
Description
From old datasheet system 4-BIT PARALLEL/ SERIAL CONVERTER