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ICS
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| Part No. |
ICS8702
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| OCR Text |
lvcmos CLOCK GENERATOR
FEATURES
* 20 lvcmos outputs, 7 typical output impedance * 1 differential clock input pair * CLK, nCLK supports the following input types: lvds, lvpecl, LVHSTL, SSTL, HCSL * Maximum output frequency up to 250MHz * T... |
| Description |
Low Skew, ÷1, ÷2, Clock Generator
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| File Size |
88.01K /
15 Page |
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ICS
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| Part No. |
ICS873034
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| OCR Text |
...rs and the outputs are enabled. lvcmos/LVTTL interface levels. Bias voltage. Pullup/ Clock input. Defaults to VCC/2 (.66) when left open. LV...lvds
C1
PCLK
R5 100
C2
VBB nPCLK
Zo = 50 Ohm
HiPerClockS PCLK/nPCLK
PC L K /n PC... |
| Description |
Low Skew, ÷2, ÷4, ÷8, Differential-to-lvpecl Clock Generator. Industrial Temperature.
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| File Size |
256.16K /
16 Page |
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ICS
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| Part No. |
ICS8732-01
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| OCR Text |
...ble differential CLK0, nCLK0 or lvcmos/LVTTL CLK1 inputs * CLK0, nCLK0 supports the following input types: lvpecl, lvds, LVHSTL, SSTL, HCSL * CLK1 accepts the following input levels: lvcmos or LVTTL * Maximum output frequency: 350MHz * VCO ... |
| Description |
Low Skew, 1-to-10, lvpecl Clock Multiplier/Zero Delay Buffer
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| File Size |
145.68K /
16 Page |
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it Online |
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ICS
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| Part No. |
ICS87322BI
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| OCR Text |
...rs and the outputs are enabled. lvcmos / LVTTL interface levels. Selects divide value for Bank A output as described in Table 3C. lvcmos / L...lvds C1
3.3V 3.3V R3 1K R4 1K PCLK
R4 125
nPCLK
HiPerClockS PC L K/n PCL K
R1 1K
R... |
| Description |
Low Skew, ÷1, ÷2 Clock Generator. Industrial Temperature.
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| File Size |
149.45K /
15 Page |
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it Online |
Download Datasheet |
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ICS
Integrated Device Technology, Inc.
INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
M1020 M1021 M1021-13-161.1328LF M1021-13I161.1328LF M1020-11-155.5200LF M1020-11I167.3280LF
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| OCR Text |
...lvpecl, as well as single-ended lvcmos, LVTTL Loss of Lock (LOL) output pin Narrow Bandwidth control input (NBW pin) Hitless Switching (H...lvds available). Clock output 0. Differential lvpecl (CML, lvds available).
, P divider selection... |
| Description |
Frequency Translation PLL Family with Loss of Lock indicator and Hitless Switching options
ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36 9 X 9 MM, CERAMIC, LCC-36
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| File Size |
307.50K /
10 Page |
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Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
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| Part No. |
MAX9173
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| OCR Text |
...l inputs and translates them to lvcmos/LVTTL outputs. The MAX9173 inputs are high impedance and require an external termination resistor whe...lvds standard. The flow-through pinout simplifies board layout and reduces crosstalk by separating t... |
| Description |
Quad lvds Line Receiver with Flow-Through Pinout and ?n-PathFail-Safe 四路lvds线接收器，引脚按信号流向排列，带有通道失效保护
Quad lvds Line Receiver with Flow- Through Pinout and “In-Path?Fail-Safe
Quad lvds Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe
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| File Size |
337.24K /
14 Page |
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it Online |
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ICS
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| Part No. |
ICS843002-31
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| OCR Text |
...put frequency: up to 700MHz * 1 lvcmos/LVTTL VCXO PLL output with output enable * 1 Reference clock output with output enable * 1 LOCK detec...lvds, LVHSTL, SSTL, HCSL or single-ended lvcmos or LVTTL levels * Singled ended inputs can support L... |
| Description |
700MHz, FemtoClock? VCXO Based Frequency Translator and Jitter Attenuator
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| File Size |
276.08K /
24 Page |
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it Online |
Download Datasheet |
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Price and Availability
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