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ALTERA
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Part No. |
EP20K100EQ EP20K100QC EP20K100EQC240-2
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OCR Text |
... differential signaling (lvds), lvpecl, PCI-X, AGP, CTT, stubseries terminated logic (SSTL-3 and SSTL-2), Gunning transceiver logic plus (GTL+), and high-speed terminated logic (HSTL Class I) - Pull-up on I/O pins before and during configur... |
Description |
Apex 20KE Device Family (1.8V, lvds Apex 20K Device Family (2.5V)
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File Size |
585.74K /
116 Page |
View
it Online |
Download Datasheet
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ICS
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Part No. |
ICS843404
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OCR Text |
lvpecl AND lvds CLOCK GENERATOR
FEATURES
* Three banks of outputs: 1 bank of 2 lvds outputs and 2 banks of 1 lvpecl output * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended reference clock input * 4 independently sele... |
Description |
Low phase noise, Fibre Channel lvpecl/lvds Clock Generator
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File Size |
235.12K /
16 Page |
View
it Online |
Download Datasheet
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Price and Availability
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