...d as 2,097,152 words x 8 bits x 4 banks. Synchronous design allows precise cycle control with the use of system clock I/O transactions are p...5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54-pin plastic TSOP II 400 mil
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... as 1,048,576 words x 16 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are p...5 ADS6616A4A-6 ADS6616A4A-7 ADS6616A4A-7.5 Frequency 200Mhz 166Mhz 143Mhz 133Mhz Interface LVTTL LVT...
...ed as 524,288 words x 32 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are p...5 ADS6632A4A-5.5 ADS6632A4A-6 Frequency 200Mhz 183Mhz 166Mhz Interface LVTTL LVTTL LVTTL Package 400...
4,194,304 words x 8 bits x 4 banks. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possib...5 ADS7608A4A-55 ADS7608A4A-6 ADS7608A4A-7 ADS7608A4A-7.5 Frequency 200Mhz 183Mhz 166Mhz 143Mhz 133Mh...
Description
Synchronous DRAM(4M X 8 Bit X 4 Banks) Synchronous DRAM(4M X 8 Bit X 4 Banks) 同步DRAM4米8位4银行 Synchronous DRAM(4M X 8 Bit X 4 Banks) 同步DRAM米8位4银行 133 Mhz LVTTL synchronous DRAM, 4 M x 8 bit x 4 banks