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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
M1010-01-155.5200LF
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| OCR Text |
... a high frequency, high-q, low phase noise os cillator that assures low intrinsic output jitter. f eatures ideal for oc-12/48 data clock ...lock d iagram figure 2: simplified block diagram example i/o clock frequency combinations using m... |
| Description |
PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36
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| File Size |
151.68K /
8 Page |
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EXAR[Exar Corporation]
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| Part No. |
XRT91L82IB XRT91L82
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| OCR Text |
...tic Buffer (FIFO) to absorb any phase differences between the transmitter clock input and the internally generated transmitter reference clo...lock detect functions and transmit CMU and receive CDR Lock Detect * Host mode serial microprocessor... |
| Description |
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
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| File Size |
388.33K /
59 Page |
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it Online |
Download Datasheet |
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NTE[NTE Electronics]
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| Part No. |
NTE989
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| OCR Text |
Phase Lock Loop (PLL)
Description: The NTE989 is a general purpose Phase Locked Loop (PLL) in a 14-Lead DIP type package containing a stable, highly linear voltage controlled oscillator for low distortion FM demodulation, and a double bala... |
| Description |
Integrated Circuit General Purpose Phase Lock Loop (PLL)
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| File Size |
26.68K /
4 Page |
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it Online |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
ICSVF2509BG
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| OCR Text |
phase-lock loop clock driver pin configuration the icsvf2509b is a high performance, low skew, low jitter clock driver. it uses a phase lock loop (pll) technology to align, in both phase and frequency, the clkin signal with the clkout sig... |
| Description |
2509 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
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| File Size |
145.38K /
9 Page |
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it Online |
Download Datasheet |
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Price and Availability
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