Description |
256 Kbit (32K x 8) nvSraM; Organization: 32Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 256 Kb; Package: SOIC 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 5; Operating range: 0 to 70 C 256K (32K x 8) static raM; Density: 256 Kb; Organization: 32Kb x 8; Vcc (V): 4.50 to 5.50 V; Three-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input range: 1 MHz to 166 MHz; Output range: 1 MHz to 200 MHz; Outputs: 6 5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 256; Vcc (V): 3.3; fMax (MHz): 66; tPD (ns): 12 8-Mbit (512k x 16) static raM; Density: 8 Mb; Organization: 512kb x 16; Vcc (V): 2.20 to 3.60 V; 9-Mbit (256K x 36/512k x 18) Pipelined SraM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; Organization: 512kb x 18; Vcc (V): 3.1 to 3.6 V 9-Mbit (256K x 36/512k x 18) Flow-Through SraM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 512kb x 18; Vcc (V): 3.1 to 3.6 V 18-Mbit QDR(TM)-II SraM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 512kb x 36; Vcc (V): 1.7 to 1.9 V Four Output PCI-x and General Purpose Buffer; Voltage (V): 3.3 V; Frequency range: 0 MHz to 140 MHz; Outputs: 4; Operating range: 0 to 70 C 18-Mbit QDR(TM)-II SraM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 512kb x 36; Vcc (V): 1.7 to 1.9 V 9-Mbit (256K x 36/512k x 18) Flow-Through SraM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 9 Mb; Organization: 512kb x 18; Vcc (V): 3.1 to 3.6 V 9-Mbit (256K x 36/512k x 18) Pipelined SraM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 512kb x 18; Vcc (V): 2.4 to 2.6 V 4-mbit (512k x 8) static raM; Density: 4 Mb; Organization: 512kb x 8; Vcc (V): 4.50 to 5.50 V; 4-mbit (256K x 16) static raM; Density: 4 Mb; Organization: 256Kb x 16; Vcc (V): 2.20 to 3.60 V; 64K x 16 static raM; Density: 1 Mb; Organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V; 1-Mbit (64K x 16) static raM; Density: 1 Mb; Organization: 64Kb x 16; Vcc (V): 4.5 to 5.5 V; 9-Mbit (256K x 36/512k x 18) Pipelined SraM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V 1-Mbit (64K x 16) static raM; Density: 1 Mb; Organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V; 4 Mbit (512k x 8/256K x 16) nvSraM; Organization: 512kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP 4 Mbit (512k x 8/256K x 16) nvSraM; Organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP 16-Mbit (1M x 16 / 2M x 8) static raM; Density: 16 Mb; Organization: 1Mb x 16; Vcc (V): 4.50 to 5.50 V; 4K x 16/18 and 8K x 16/18 Dual-Port static raM with SEM, INT, BUSY; Density: 128 Kb; Organization: 8Kb x 16; Vcc (V): 4.5 to 5.5 V; Speed: 35 ns 9-Mbit (256K x 36/512k x 18) Pipelined SraM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V 9-Mbit (256K x 36/512k x 18) Flow-Through SraM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V 9-Mbit (256K x 36/512k x 18) Pipelined SraM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 2.4 to 2.6 V 9-Mbit (256K x 36/512k x 18) Pipelined SraM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 512kb x 18; Vcc (V): 3.1 to 3.6 V 8-Mbit (512k x 16) static raM; Density: 8 Mb; Organization: 512kb x 16; Vcc (V): 4.50 to 5.50 V; 9-Mbit (256K x 36/512k x 18) Flow-Through SraM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V 256K x 16 static raM; Density: 4 Mb; Organization: 256Kb x 16; Vcc (V): 4.5 to 5.5 V; 9-Mbit (256K x 36/512k x 18) Pipelined DCD Sync SraM; Architecture: Standard Sync, Pipeline DCD; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V 4-mbit (256K x 16) static raM; Density: 4 Mb; Organization: 256Kb x 16; Vcc (V): 3.0 to 3.6 V; 8-Mbit (1024K x 8) static raM; Density: 8 Mb; Organization: 1Mb x 8; Vcc (V): 2.20 to 3.60 V; 18-Mbit (512k x 36/1M x 18) Pipelined SraM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512kb x 36; Vcc (V): 3.1 to 3.6 V 256K x 16 static raM; Density: 4 Mb; Organization: 256Kb x 16; Vcc (V): 3.0 to 3.6 V; 8-Mbit (1M x 8) static raM; Density: 8 Mb; Organization: 1Mb x 8; Vcc (V): 2.20 to 3.60 V; 3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 8; Operating range: -40 to 85 C Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating range: -40 to 85 C 18-Mbit (512k x 36/1M x 18) Flow-Through SraM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 18 Mb; Organization: 512kb x 36; Vcc (V): 3.1 to 3.6 V 18-Mbit (512k x 36/1M x 18) Pipelined SraM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 512k x 8 static raM; Density: 4 Mb; Organization: 512kb x 8; Vcc (V): 4.5 to 5.5 V; 18-Mbit (512k x 36/1M x 18) Pipelined SraM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512kb x 36; Vcc (V): 2.4 to 2.6 V 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: 12; Operating range: -40 to 85 C 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 5; Operating range: -40 to 85 C 2M x 8 static raM; Density: 16 Mb; Organization: 2Mb x 8; Vcc (V): 3.0 to 3.6 V; 16 Mbit (512k x 32) static raM; Density: 16 Mb; Organization: 512kb x 32; Vcc (V): 3.0 to 3.6 V; 3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 8; Operating range: 0 to 70 C 8-Mbit (1M x 8) static raM; Density: 8 Mb; Organization: 1Mb x 8; Vcc (V): 3.0 to 3.6 V; 5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6 2-Mbit (128K x 16) static raM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V; 16-Mbit (1M x 16) static raM; Density: 16 Mb; Organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V; 4-mbit (256K x 18) Pipelined DCD Sync SraM; Architecture: Standard Sync, Pipeline DCD; Density: 4 Mb; Organization: 256Kb x 18; Vcc (V): 3.1 to 3.6 V 512k (32K x 16) static raM; Density: 512 Kb; Organization: 32Kb x 16; Vcc (V): 3.0 to 3.6 V; 4-mbit (128K x 36) Pipelined SraM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 4 Mb; Organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V 1M x 16 static raM; Density: 16 Mb; Organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V; Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating range: 0 to 70 C 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 9; Operating range: 0 to 70 C mobl(R) 2 Mbit (128K x 16) static raM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V; rambus(R) xDR(TM) Clock Generator; VDD: 2.5 V; Input Frequency: 100 MHz to 133 MHz; Output Frequency: 300 MHz to 800 MHz; # Out: 4 2-Mbit (128K x 16) static raM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V; 4-mbit (128K x 36) Pipelined Sync SraM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; Organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V 5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 167; tPD (ns): 7 2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: 10; Operating range: 0 to 70 C 5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 100; tPD (ns): 7 5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 7 18-Mbit DDR-II SraM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 18 Mb; Organization: 512kb x 36; Vcc (V): 1.7 to 1.9 V Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating range: 0 to 70 C Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency range: 25 MHz to 100 MHz; Output Frequency range: 25 MHz to 100 MHz; Operating range: 0 to 70 C; Package: SOIC Low Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating range: 0 to 70 C 5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 143; tPD (ns): 9 单芯位CMOS微机 5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 154; tPD (ns): 6 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机 5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9 单芯位CMOS微机 5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 128; Vcc (V): 3.3; fMax (MHz): 83; tPD (ns): 10 单芯位CMOS微机 5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6 单芯位CMOS微机 Three-PLL General-Purpose EPROM Programmable Clock Generator; Voltage (V): 3.3/5.0 V; Input range: 1 MHz to 30 MHz; Output range: .077 MHz to 100 MHz; Outputs: 6 单芯位CMOS微机 8-Mbit (512k x 16) mobl(R) static raM; Density: 8 Mb; Organization: 512kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机 High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating range: 0 to 70 C 单芯位CMOS微机 3.3V SDraM Buffer for Mobile PCs with 4 SO-DIMMs; Voltage (V): 3.3 V; Frequency range: 0 MHz to 100 MHz; Outputs: 10; Operating range: 0 to 70 C 单芯位CMOS微机 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 9; Operating range: -40 to 85 C 单芯位CMOS微机 Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating range: -40 to 85 C 单芯位CMOS微机 2-Mbit (128K x 16) static raM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V; 单芯位CMOS微机 mobl(R) 1 Mbit (128K x 8) static raM; Density: 1 Mb; Organization: 128Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机 18-Mbit QDR(TM)-II SraM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 1-Mbit (128K x 8) static raM; Density: 1 Mb; Organization: 128Kb x 8; Vcc (V): 4.50 to 5.50 V; 单芯位CMOS微机 4-mbit (256K x 18) Pipelined Sync SraM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; Organization: 256Kb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 2-Mbit (64K x 32) Pipelined Sync SraM; Architecture: Standard Sync, Pipeline SCD; Density: 2 Mb; Organization: 64Kb x 32; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 200-MHz Field Programmable Zero Delay Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 10 MHz to 200 MHz; Outputs: 12; Operating range: -40 to 85 C 单芯位CMOS微机 2-Mbit (128K x 16) static raM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机 2-Mbit (256K x 8) static raM; Density: 2 Mb; Organization: 256Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯8位CMOS微机 Very Low Jitter Field and Factory Programmable Clock Generator; Voltage (V): 3.3 V; Input range: 10 MHz to 133 MHz; Output range: 20 MHz to 200 MHz; Outputs: 2 单芯位CMOS微机 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 5; Operating range: 0 to 70 C 单芯位CMOS微机 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 5; Operating range: -40 to 85 C 单芯位CMOS微机 Three-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input range: 1 MHz to 166 MHz; Output range: 0 MHz to 200 MHz; Outputs: 3 单芯位CMOS微机 1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency range: 0 MHz to 350 MHz; Outputs: 8; Operating range: -40 to 85 C 单芯位CMOS微机 Quad PLL Clock Generator with 2-Wire Serial Interface; Voltage (V): 2.5/3.3 V; Input range: 27 MHz to 27 MHz; Output range: 4.2 MHz to 166 MHz; Outputs: 5 单芯位CMOS微机 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: 12; Operating range: 0 to 70 C 单芯位CMOS微机 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 9; Operating range: 0 to 70 C 单芯位CMOS微机 High Speed Multi-phase PLL Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 24 MHz to 200 MHz; Outputs: 11; Operating range: 0 to 70 C 单芯位CMOS微机 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: 18; Operating range: -40 to 85 C 单芯位CMOS微机 -bit AVR Microcontroller with 8K Bytes In- System Programmable Flash 位AVR微控制器具有8K字节的系统内可编程闪 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: 12; Operating range: 0 to 70 C 1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency range: 0 MHz to 350 MHz; Outputs: 8; Operating range: 0 to 70 C Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency range: 4 MHz to 32 MHz; Output Frequency range: 4 MHz to 32 MHz; Operating range: 0 to 70 C; Package: SOIC High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating range: 0 to 70 C 5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9
|