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ICS
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| Part No. |
ICS843001
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| OCR Text |
... Pulldown Frequency select pin. lvcmos/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Core supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4 5 6, 7 8 Name VCCA V EE XTAL_OUT, XTAL_IN FREQ_SEL nQ0, Q0 VC... |
| Description |
FemtoClocks? Crystal-to-3.3V LVPECL Clock Generator
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| File Size |
235.59K /
15 Page |
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ICS
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| Part No. |
ICS85408I
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| OCR Text |
...nput Pullup outputs are in HiZ. lvcmos / LVTTL interface levels. 23, 24 nQ7, Q7 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typic... |
| Description |
Low Skew, 1-to-8 Differential-to-LVDS Fanout Buffer. Industrial Temp.
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| File Size |
160.19K /
12 Page |
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it Online |
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ICS
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| Part No. |
M2006-03
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| OCR Text |
...-ended reference inputs support lvcmos, LVTTL All output clocks are differential LVPECL compatible Two downstream clocks, frequency-selectable One upstream clock, frequency-selectable REF_OUT always provides a 10.24MHz reference clock ... |
| Description |
SAW PLL for Frequency Translation with Add/Drop feature and Hitless Switching option
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| File Size |
223.26K /
6 Page |
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ICS
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| Part No. |
M2006-04
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| OCR Text |
...LVPECL, as well as single-ended lvcmos, LVTTL Power-up frequency translation ratio of x32 useful for 19.44MHz input and 155.52 or 622.08MHz output Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assig... |
| Description |
VCSO Frequency Translator
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| File Size |
300.56K /
12 Page |
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it Online |
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ICS
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| Part No. |
M2006-11 M2006-21 M2006-11-622.0800
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| OCR Text |
...LVPECL, as well as single-ended lvcmos, LVTTL
Figure 1: Pin Assignment
Example Input / Output Frequency Combinations
Input Clock VCSO Output (MHz) Freq1 (MHz) Freq (MHz) 19.44 19.53125 622.08 625.00 622.08 155.52 156.25 Gigabit Ether... |
| Description |
PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36
SAW PLL for Frequency Translation with Add/Drop feature and Hitless Switching option
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| File Size |
312.67K /
14 Page |
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Integrated Circuit System
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| Part No. |
M2006-12
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| OCR Text |
...ial LVPECL. P Divider controls. lvcmos/LVTTL. (For P0_SEL, P1_SEL, see Table 5 on pg. 3. Reference clock input pair 1. Differential LVPECL or LVDS. Reference clock input selection. lvcmos/LVTTL: Logic 1 selects DIF_REF1, nDIF_REF1. Logic 0 ... |
| Description |
VCSO BASED FEC CLOCK PLL
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| File Size |
262.41K /
8 Page |
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it Online |
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