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AGERE[Agere Systems]
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Part No. |
LCK4310 LCK4310GF-DT LCK4310GF-DB
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OCR Text |
...he backplane or the board. In a pecl environment (series or Thevenin), line terminations are typically used since they require no additional...LVpecl 3.3 V dc Characteristics VDD = 3.3 V, VEE = 0 V. Input and output parameters vary 1:1 with VD... |
Description |
Low-Voltage PLL Clock Driver
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File Size |
63.46K /
10 Page |
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Cypress Semiconductor Corp. CYPRESS[Cypress Semiconductor]
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Part No. |
CY2DP314 CY2DP314OI CY2DP314OIT CY2DP314OXI CY2DP314OXIT
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OCR Text |
pecl differential outputs * One ecl/pecl differential or single-ended inputs (CLKA) * One HSTL differential or single-ended inputs (CLKB) * ...LVpecl Output
In p u t C lo c k
VPP
TPLH, TPD O u tp u t C lo c k TPHL
VO
tS K (O )
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Description |
VGA VIDEO SPLITTER 10-CH INCLU 1 of 2:4 Differential Clock/Data Fanout Buffer
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File Size |
211.09K /
9 Page |
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it Online |
Download Datasheet
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Micrel Semiconductor, Inc.
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Part No. |
SY100EP58VZI SY100EP58VZITR
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OCR Text |
...: /0 issue date: july 2005 2:1 pecl/ecl multiplexer guaranteed acCperformance over temperature/voltage ? >3ghz f max (toggle) ? <200ps ri...lvpecl mode. the sy100ep58v is internally temperature compensated, thus is 100k ep ecl/pecl compatib... |
Description |
3.3V/5V 3GHz pecl/ecl 2:1 MULTIPLEXER 100E SERIES, 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO8
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File Size |
822.87K /
9 Page |
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it Online |
Download Datasheet
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Price and Availability
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